Assert Coverage for Module :
usbdev_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
11757 |
0 |
0 |
T203 |
5487 |
8 |
0 |
0 |
T204 |
6417 |
6 |
0 |
0 |
T205 |
4244 |
9 |
0 |
0 |
T227 |
40622 |
7 |
0 |
0 |
T228 |
19501 |
3 |
0 |
0 |
T229 |
26768 |
3 |
0 |
0 |
T235 |
8556 |
8 |
0 |
0 |
T236 |
3204 |
24 |
0 |
0 |
T250 |
3711 |
13 |
0 |
0 |
T251 |
11409 |
23 |
0 |
0 |
ep_in_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
3199 |
0 |
0 |
T203 |
5487 |
2 |
0 |
0 |
T208 |
11670 |
30 |
0 |
0 |
T227 |
40622 |
154 |
0 |
0 |
T229 |
26768 |
245 |
0 |
0 |
T235 |
8556 |
18 |
0 |
0 |
T251 |
11409 |
43 |
0 |
0 |
T259 |
37786 |
231 |
0 |
0 |
T265 |
2944 |
50 |
0 |
0 |
T270 |
4319 |
100 |
0 |
0 |
T277 |
26744 |
162 |
0 |
0 |
ep_out_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
3282 |
0 |
0 |
T203 |
5487 |
8 |
0 |
0 |
T208 |
11670 |
20 |
0 |
0 |
T227 |
40622 |
149 |
0 |
0 |
T229 |
26768 |
279 |
0 |
0 |
T235 |
8556 |
24 |
0 |
0 |
T251 |
11409 |
13 |
0 |
0 |
T259 |
37786 |
260 |
0 |
0 |
T265 |
2944 |
6 |
0 |
0 |
T270 |
4319 |
58 |
0 |
0 |
T277 |
26744 |
91 |
0 |
0 |
in_iso_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
3585 |
0 |
0 |
T203 |
5487 |
8 |
0 |
0 |
T208 |
11670 |
20 |
0 |
0 |
T227 |
40622 |
219 |
0 |
0 |
T229 |
26768 |
342 |
0 |
0 |
T235 |
8556 |
28 |
0 |
0 |
T251 |
11409 |
45 |
0 |
0 |
T259 |
37786 |
259 |
0 |
0 |
T265 |
2944 |
43 |
0 |
0 |
T270 |
4319 |
40 |
0 |
0 |
T277 |
26744 |
169 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
5079 |
0 |
0 |
T203 |
5487 |
6 |
0 |
0 |
T208 |
11670 |
11 |
0 |
0 |
T213 |
1677 |
6 |
0 |
0 |
T227 |
40622 |
444 |
0 |
0 |
T229 |
26768 |
299 |
0 |
0 |
T251 |
11409 |
111 |
0 |
0 |
T259 |
37786 |
258 |
0 |
0 |
T270 |
4319 |
97 |
0 |
0 |
T278 |
3940 |
15 |
0 |
0 |
T279 |
1981 |
10 |
0 |
0 |
out_iso_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
3449 |
0 |
0 |
T203 |
5487 |
57 |
0 |
0 |
T208 |
11670 |
35 |
0 |
0 |
T227 |
40622 |
229 |
0 |
0 |
T229 |
26768 |
307 |
0 |
0 |
T235 |
8556 |
2 |
0 |
0 |
T251 |
11409 |
53 |
0 |
0 |
T259 |
37786 |
248 |
0 |
0 |
T265 |
2944 |
9 |
0 |
0 |
T270 |
4319 |
29 |
0 |
0 |
T277 |
26744 |
205 |
0 |
0 |
phy_config_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
1930 |
0 |
0 |
T203 |
5487 |
26 |
0 |
0 |
T208 |
11670 |
12 |
0 |
0 |
T227 |
40622 |
139 |
0 |
0 |
T229 |
26768 |
93 |
0 |
0 |
T235 |
8556 |
26 |
0 |
0 |
T251 |
11409 |
25 |
0 |
0 |
T259 |
37786 |
236 |
0 |
0 |
T265 |
2944 |
28 |
0 |
0 |
T270 |
4319 |
28 |
0 |
0 |
T277 |
26744 |
60 |
0 |
0 |
phy_pins_drive_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
2449 |
0 |
0 |
T203 |
5487 |
8 |
0 |
0 |
T208 |
11670 |
13 |
0 |
0 |
T227 |
40622 |
261 |
0 |
0 |
T229 |
26768 |
125 |
0 |
0 |
T235 |
8556 |
6 |
0 |
0 |
T251 |
11409 |
63 |
0 |
0 |
T259 |
37786 |
166 |
0 |
0 |
T265 |
2944 |
1 |
0 |
0 |
T270 |
4319 |
40 |
0 |
0 |
T277 |
26744 |
94 |
0 |
0 |
rxenable_setup_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
3101 |
0 |
0 |
T203 |
5487 |
59 |
0 |
0 |
T208 |
11670 |
28 |
0 |
0 |
T227 |
40622 |
283 |
0 |
0 |
T229 |
26768 |
116 |
0 |
0 |
T235 |
8556 |
15 |
0 |
0 |
T251 |
11409 |
19 |
0 |
0 |
T259 |
37786 |
207 |
0 |
0 |
T265 |
2944 |
7 |
0 |
0 |
T270 |
4319 |
13 |
0 |
0 |
T277 |
26744 |
163 |
0 |
0 |
set_nak_out_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400902668 |
3463 |
0 |
0 |
T203 |
5487 |
10 |
0 |
0 |
T208 |
11670 |
15 |
0 |
0 |
T227 |
40622 |
353 |
0 |
0 |
T229 |
26768 |
289 |
0 |
0 |
T235 |
8556 |
16 |
0 |
0 |
T251 |
11409 |
49 |
0 |
0 |
T259 |
37786 |
226 |
0 |
0 |
T265 |
2944 |
4 |
0 |
0 |
T270 |
4319 |
33 |
0 |
0 |
T277 |
26744 |
218 |
0 |
0 |