Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16406933	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16754340	1		T1	15		T2	8		T3	21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32626897	1		T1	10		T2	7		T3	63
values[0x0]	266630	1		T1	10		T2	4		T3	18
values[0x1]	267746	1		T1	6		T2	3		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13078720	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20082553	1		T1	18		T2	9		T3	42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	97028	1		T4	151		T5	126		T33	162
valid_sources[0x01]	442771	1		T4	192		T5	114		T33	192
valid_sources[0x02]	97539	1		T4	158		T5	142		T33	182
valid_sources[0x03]	96515	1		T4	112		T5	161		T33	196
valid_sources[0x04]	96411	1		T4	192		T5	152		T33	257
valid_sources[0x05]	233116	1		T4	237		T5	116		T33	226
valid_sources[0x06]	389084	1		T4	114		T5	166		T33	323
valid_sources[0x07]	95587	1		T4	158		T5	169		T33	284
valid_sources[0x08]	93715	1		T4	158		T5	154		T33	226
valid_sources[0x09]	94981	1		T4	160		T5	152		T33	264
valid_sources[0x0a]	97099	1		T4	144		T5	132		T33	254
valid_sources[0x0b]	98423	1		T4	203		T5	168		T33	182
valid_sources[0x0c]	98577	1		T4	163		T5	166		T33	192
valid_sources[0x0d]	94827	1		T4	147		T5	160		T33	219
valid_sources[0x0e]	96327	1		T4	150		T5	123		T33	241
valid_sources[0x0f]	96765	1		T3	3		T4	162		T5	155
valid_sources[0x10]	95042	1		T4	173		T5	144		T33	144
valid_sources[0x11]	235111	1		T4	131		T5	143		T33	237
valid_sources[0x12]	97469	1		T4	223		T5	159		T33	197
valid_sources[0x13]	96302	1		T30	1		T4	120		T5	116
valid_sources[0x14]	95964	1		T4	149		T5	152		T33	254
valid_sources[0x15]	97399	1		T4	202		T5	139		T33	327
valid_sources[0x16]	99126	1		T4	199		T5	124		T33	285
valid_sources[0x17]	200268	1		T4	184		T5	139		T33	235
valid_sources[0x18]	97505	1		T4	177		T5	137		T33	269
valid_sources[0x19]	96613	1		T3	3		T4	181		T5	152
valid_sources[0x1a]	95525	1		T4	232		T5	133		T33	247
valid_sources[0x1b]	95735	1		T4	138		T5	154		T33	167
valid_sources[0x1c]	124720	1		T2	2		T4	143		T5	159
valid_sources[0x1d]	97823	1		T4	179		T5	164		T33	323
valid_sources[0x1e]	96607	1		T4	221		T5	150		T33	282
valid_sources[0x1f]	750035	1		T4	123		T5	147		T33	223
valid_sources[0x20]	95365	1		T4	207		T5	151		T33	209
valid_sources[0x21]	118972	1		T3	8		T4	116		T5	155
valid_sources[0x22]	95605	1		T3	3		T4	229		T5	145
valid_sources[0x23]	97162	1		T4	173		T5	156		T33	212
valid_sources[0x24]	97231	1		T4	173		T5	149		T33	257
valid_sources[0x25]	94370	1		T4	171		T5	129		T33	267
valid_sources[0x26]	96749	1		T2	1		T4	139		T5	147
valid_sources[0x27]	327025	1		T4	137		T5	139		T33	157
valid_sources[0x28]	94333	1		T4	149		T5	162		T33	204
valid_sources[0x29]	97271	1		T4	174		T5	161		T33	258
valid_sources[0x2a]	340144	1		T4	227		T5	141		T33	193
valid_sources[0x2b]	96754	1		T1	3		T4	203		T5	135
valid_sources[0x2c]	94773	1		T4	153		T5	145		T33	235
valid_sources[0x2d]	167080	1		T4	153		T5	138		T33	252
valid_sources[0x2e]	97080	1		T4	243		T5	145		T33	202
valid_sources[0x2f]	93767	1		T4	178		T5	164		T33	188
valid_sources[0x30]	123594	1		T4	226		T5	148		T33	295
valid_sources[0x31]	95159	1		T4	161		T5	164		T33	219
valid_sources[0x32]	95682	1		T4	127		T5	133		T33	363
valid_sources[0x33]	95241	1		T4	225		T5	169		T33	197
valid_sources[0x34]	95713	1		T4	142		T5	161		T33	212
valid_sources[0x35]	159073	1		T4	132		T5	135		T31	1
valid_sources[0x36]	129921	1		T4	198		T5	143		T33	260
valid_sources[0x37]	122379	1		T4	205		T5	146		T33	318
valid_sources[0x38]	131448	1		T4	152		T5	149		T33	147
valid_sources[0x39]	156787	1		T4	159		T5	160		T33	298
valid_sources[0x3a]	101206	1		T4	113		T5	166		T33	210
valid_sources[0x3b]	95874	1		T4	151		T5	158		T33	251
valid_sources[0x3c]	95137	1		T4	106		T5	123		T33	218
valid_sources[0x3d]	97450	1		T30	1		T4	171		T5	154
valid_sources[0x3e]	307179	1		T1	6		T4	144		T5	144
valid_sources[0x3f]	96198	1		T4	195		T5	156		T31	1
valid_sources[0x40]	97968	1		T4	176		T5	138		T33	252
valid_sources[0x41]	183151	1		T30	1		T4	177		T5	161
valid_sources[0x42]	143157	1		T4	160		T5	133		T33	218
valid_sources[0x43]	164536	1		T4	145		T5	162		T32	1
valid_sources[0x44]	94649	1		T4	198		T5	147		T33	222
valid_sources[0x45]	97129	1		T4	157		T5	138		T33	226
valid_sources[0x46]	96124	1		T4	153		T5	147		T33	228
valid_sources[0x47]	194359	1		T4	269		T5	135		T33	173
valid_sources[0x48]	96462	1		T4	131		T5	145		T33	329
valid_sources[0x49]	96135	1		T4	229		T5	143		T33	177
valid_sources[0x4a]	141698	1		T4	174		T5	154		T33	234
valid_sources[0x4b]	234365	1		T3	2		T29	48		T4	131
valid_sources[0x4c]	184999	1		T4	91		T5	148		T33	235
valid_sources[0x4d]	184881	1		T4	152		T5	146		T33	241
valid_sources[0x4e]	99392	1		T4	223		T5	168		T33	261
valid_sources[0x4f]	97089	1		T3	1		T4	203		T5	164
valid_sources[0x50]	202915	1		T4	205		T5	151		T33	219
valid_sources[0x51]	96027	1		T4	263		T5	143		T33	223
valid_sources[0x52]	100039	1		T4	181		T5	144		T33	197
valid_sources[0x53]	95584	1		T4	162		T5	164		T33	282
valid_sources[0x54]	98332	1		T4	97		T5	137		T33	219
valid_sources[0x55]	97610	1		T4	226		T5	138		T33	281
valid_sources[0x56]	262500	1		T4	149		T5	158		T33	290
valid_sources[0x57]	96755	1		T3	5		T4	154		T5	142
valid_sources[0x58]	97535	1		T4	157		T5	165		T33	228
valid_sources[0x59]	95338	1		T4	145		T5	140		T33	195
valid_sources[0x5a]	98069	1		T4	146		T5	169		T33	203
valid_sources[0x5b]	137909	1		T4	242		T5	173		T33	206
valid_sources[0x5c]	96512	1		T4	160		T5	127		T33	199
valid_sources[0x5d]	98575	1		T4	131		T5	156		T33	221
valid_sources[0x5e]	95387	1		T4	183		T5	134		T33	254
valid_sources[0x5f]	97548	1		T3	9		T4	177		T5	156
valid_sources[0x60]	96818	1		T4	166		T5	160		T31	1
valid_sources[0x61]	122023	1		T4	146		T5	162		T33	189
valid_sources[0x62]	97269	1		T4	184		T5	142		T33	280
valid_sources[0x63]	99189	1		T4	184		T5	150		T33	244
valid_sources[0x64]	93358	1		T4	98		T5	164		T33	256
valid_sources[0x65]	99520	1		T4	270		T5	146		T33	191
valid_sources[0x66]	95454	1		T4	185		T5	133		T33	175
valid_sources[0x67]	152541	1		T3	8		T4	155		T5	129
valid_sources[0x68]	96701	1		T28	4		T4	203		T5	136
valid_sources[0x69]	96661	1		T4	165		T5	148		T33	147
valid_sources[0x6a]	95598	1		T4	156		T5	154		T33	223
valid_sources[0x6b]	100005	1		T4	149		T5	165		T33	286
valid_sources[0x6c]	96960	1		T3	2		T4	134		T5	151
valid_sources[0x6d]	97498	1		T4	184		T5	176		T33	240
valid_sources[0x6e]	98609	1		T4	212		T5	167		T33	178
valid_sources[0x6f]	93550	1		T4	210		T5	128		T33	247
valid_sources[0x70]	97048	1		T4	199		T5	176		T33	158
valid_sources[0x71]	96934	1		T4	183		T5	134		T33	182
valid_sources[0x72]	138489	1		T1	6		T3	3		T4	170
valid_sources[0x73]	96104	1		T3	6		T4	153		T5	135
valid_sources[0x74]	449219	1		T4	180		T5	146		T33	275
valid_sources[0x75]	96658	1		T3	1		T4	241		T5	172
valid_sources[0x76]	96026	1		T1	9		T4	201		T5	182
valid_sources[0x77]	97933	1		T4	126		T5	155		T33	214
valid_sources[0x78]	94971	1		T4	187		T5	132		T33	195
valid_sources[0x79]	120872	1		T4	196		T5	129		T33	196
valid_sources[0x7a]	95594	1		T4	244		T5	133		T33	271
valid_sources[0x7b]	97327	1		T4	170		T5	152		T33	281
valid_sources[0x7c]	97157	1		T4	150		T5	153		T31	1
valid_sources[0x7d]	99422	1		T4	149		T5	145		T33	294
valid_sources[0x7e]	97728	1		T4	191		T5	171		T33	237
valid_sources[0x7f]	95445	1		T30	1		T4	192		T5	158
valid_sources[0x80]	94093	1		T4	170		T5	157		T32	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16338401

1

T1

4

T2

5

T3

4

values[0x0]

all_enables

biggest_size

214826

1

T1

7

T2

2

T3

13

values[0x1]

all_enables

biggest_size

201113

1

T1

4

T2

1

T3

4