Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16422220	1		T1	11		T2	6		T3	67
full_word	16755401	1		T1	15		T2	8		T3	21

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33177301	1		T1	26		T2	14		T3	88
auto[TlIntgErrCmd]	105	1		T194	7		T223	3		T224	3
auto[TlIntgErrData]	102	1		T194	6		T223	2		T224	3
auto[TlIntgErrBoth]	113	1		T194	7		T223	5		T224	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32628812	1		T1	10		T2	7		T3	63
auto[1]	548809	1		T1	16		T2	7		T3	25

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16290110	1		T1	6		T2	2		T3	59
auto[TlIntgErrNone]	partial	auto[1]	131815	1		T1	5		T2	4		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	16338571	1		T1	4		T2	5		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	416805	1		T1	11		T2	3		T3	17
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T194	1		T223	1		T224	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T194	6		T223	2		T224	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T287	1		T265	1		T289	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T265	1		T290	1		T291	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T194	5		T224	1		T286	2
auto[TlIntgErrData]	partial	auto[1]	51	1		T194	1		T223	2		T224	2
auto[TlIntgErrData]	full_word	auto[0]	1	1		T292	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1		T236	1		T265	1		T291	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T194	3		T223	3		T224	1
auto[TlIntgErrBoth]	partial	auto[1]	63	1		T194	4		T223	2		T224	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T236	1		T288	1		T293	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T224	1		T236	1		T287	1