Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.73	97.53	86.57	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	388820213	12408	0	0
ep_in_enable_rd_A	388820213	3380	0	0
ep_out_enable_rd_A	388820213	3158	0	0
in_iso_rd_A	388820213	3083	0	0
intr_enable_rd_A	388820213	4590	0	0
out_iso_rd_A	388820213	3785	0	0
phy_config_rd_A	388820213	1994	0	0
phy_pins_drive_rd_A	388820213	2604	0	0
rxenable_setup_rd_A	388820213	3116	0	0
set_nak_out_rd_A	388820213	3637	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	12408	0	0
T194	46854	6	0	0
T195	19522	1013	0	0
T196	6334	15	0	0
T198	9322	15	0	0
T218	10626	823	0	0
T223	36926	2	0	0
T224	22802	1	0	0
T225	10397	563	0	0
T229	5153	23	0	0
T232	3187	11	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	3380	0	0
T194	46854	473	0	0
T198	9322	54	0	0
T223	36926	283	0	0
T224	22802	203	0	0
T236	21437	410	0	0
T256	3815	41	0	0
T261	3953	15	0	0
T262	39583	510	0	0
T263	13674	1	0	0
T264	14267	18	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	3158	0	0
T194	46854	548	0	0
T198	9322	35	0	0
T223	36926	139	0	0
T224	22802	223	0	0
T236	21437	103	0	0
T248	3900	33	0	0
T256	3815	61	0	0
T261	3953	39	0	0
T262	39583	319	0	0
T264	14267	1	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	3083	0	0
T194	46854	331	0	0
T198	9322	21	0	0
T223	36926	147	0	0
T224	22802	257	0	0
T236	21437	66	0	0
T248	3900	1	0	0
T256	3815	49	0	0
T262	39583	521	0	0
T264	14267	7	0	0
T265	70705	340	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	4590	0	0
T194	46854	478	0	0
T198	9322	99	0	0
T204	2565	23	0	0
T205	3635	1	0	0
T223	36926	401	0	0
T224	22802	298	0	0
T236	21437	485	0	0
T256	3815	74	0	0
T266	3816	21	0	0
T267	2929	7	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	3785	0	0
T194	46854	522	0	0
T198	9322	67	0	0
T223	36926	268	0	0
T224	22802	185	0	0
T236	21437	279	0	0
T256	3815	15	0	0
T261	3953	41	0	0
T262	39583	617	0	0
T264	14267	18	0	0
T265	70705	312	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	1994	0	0
T194	46854	225	0	0
T198	9322	46	0	0
T223	36926	79	0	0
T224	22802	154	0	0
T230	16172	1	0	0
T236	21437	154	0	0
T256	3815	25	0	0
T261	3953	21	0	0
T262	39583	290	0	0
T264	14267	55	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	2604	0	0
T194	46854	520	0	0
T198	9322	110	0	0
T223	36926	212	0	0
T224	22802	198	0	0
T236	21437	197	0	0
T248	3900	22	0	0
T256	3815	33	0	0
T261	3953	3	0	0
T262	39583	316	0	0
T264	14267	14	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	3116	0	0
T194	46854	514	0	0
T195	19522	8	0	0
T198	9322	106	0	0
T223	36926	152	0	0
T224	22802	171	0	0
T236	21437	203	0	0
T256	3815	56	0	0
T261	3953	50	0	0
T262	39583	500	0	0
T264	14267	49	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388820213	3637	0	0
T194	46854	467	0	0
T198	9322	85	0	0
T223	36926	354	0	0
T224	22802	269	0	0
T236	21437	207	0	0
T248	3900	48	0	0
T256	3815	74	0	0
T261	3953	30	0	0
T262	39583	700	0	0
T264	14267	19	0	0