Module Definition
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Module Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
54.76 85.71 33.33 100.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
56.41 92.31 33.33 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.40 94.12 46.15 83.33 50.00 u_wake_events_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wake_control_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.67 33.33 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T9
10CoveredT7,T8,T9
11CoveredT7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T9
10CoveredT7,T8,T9
11CoveredT7,T8,T9

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 398143433 2402 0 0
SrcPulseCheck_M 782302036 2426 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 398143433 2402 0 0
T7 134689 4 0 0
T8 179532 4 0 0
T9 0 4 0 0
T10 0 4 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T14 0 4 0 0
T15 0 4 0 0
T16 0 4 0 0
T17 161304 0 0 0
T18 160511 0 0 0
T19 8472 0 0 0
T20 7405 0 0 0
T21 11335 0 0 0
T22 10732 0 0 0
T23 10153 0 0 0
T24 15824 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 782302036 2426 0 0
T7 134689 4 0 0
T8 179532 4 0 0
T9 0 4 0 0
T10 0 4 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T14 0 4 0 0
T15 0 4 0 0
T16 0 4 0 0
T17 161304 0 0 0
T18 160511 0 0 0
T19 8472 0 0 0
T20 7405 0 0 0
T21 11335 0 0 0
T22 10732 0 0 0
T23 10153 0 0 0
T24 15824 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN97100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 0 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions6233.33
Logical6233.33
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Not Covered
11Unreachable

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 4661610 0 0 0
SrcPulseCheck_M 388820213 0 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4661610 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 388820213 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T9
10CoveredT7,T8,T9
11CoveredT7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T9
10CoveredT7,T8,T9
11CoveredT7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 4661610 1196 0 0
SrcPulseCheck_M 388820213 1220 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4661610 1196 0 0
T7 22719 2 0 0
T8 2237 2 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 2 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 0 2 0 0
T15 0 2 0 0
T16 0 2 0 0
T17 2286 0 0 0
T18 1550 0 0 0
T19 102 0 0 0
T20 117 0 0 0
T21 63 0 0 0
T22 184 0 0 0
T23 198 0 0 0
T24 262 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 388820213 1220 0 0
T7 111970 2 0 0
T8 177295 2 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 2 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 0 2 0 0
T15 0 2 0 0
T16 0 2 0 0
T17 159018 0 0 0
T18 158961 0 0 0
T19 8370 0 0 0
T20 7288 0 0 0
T21 11272 0 0 0
T22 10548 0 0 0
T23 9955 0 0 0
T24 15562 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T9
10CoveredT7,T8,T9
11CoveredT7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T9
10CoveredT7,T8,T9
11CoveredT7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 388820213 1206 0 0
SrcPulseCheck_M 4661610 1206 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388820213 1206 0 0
T7 111970 2 0 0
T8 177295 2 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 2 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 0 2 0 0
T15 0 2 0 0
T16 0 2 0 0
T17 159018 0 0 0
T18 158961 0 0 0
T19 8370 0 0 0
T20 7288 0 0 0
T21 11272 0 0 0
T22 10548 0 0 0
T23 9955 0 0 0
T24 15562 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 4661610 1206 0 0
T7 22719 2 0 0
T8 2237 2 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 2 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 0 2 0 0
T15 0 2 0 0
T16 0 2 0 0
T17 2286 0 0 0
T18 1550 0 0 0
T19 102 0 0 0
T20 117 0 0 0
T21 63 0 0 0
T22 184 0 0 0
T23 198 0 0 0
T24 262 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%