Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14344351	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	14661625	1		T1	365		T2	11		T3	9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28530530	1		T1	221		T2	12		T3	462
values[0x0]	237620	1		T1	489		T2	3		T3	3
values[0x1]	237826	1		T1	436		T2	8		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11434205	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	17571771	1		T1	443		T2	16		T3	178

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	84160	1		T1	9		T3	5		T4	480
valid_sources[0x01]	83337	1		T1	1		T4	473		T6	452
valid_sources[0x02]	232929	1		T1	3		T3	2		T4	441
valid_sources[0x03]	83983	1		T1	3		T4	432		T6	484
valid_sources[0x04]	83531	1		T3	1		T4	470		T6	445
valid_sources[0x05]	82134	1		T1	6		T3	2		T4	452
valid_sources[0x06]	141567	1		T1	16		T3	5		T4	446
valid_sources[0x07]	292803	1		T3	3		T4	464		T6	422
valid_sources[0x08]	219685	1		T1	2		T4	468		T6	505
valid_sources[0x09]	107481	1		T1	1		T3	2		T4	509
valid_sources[0x0a]	83875	1		T1	6		T4	511		T6	462
valid_sources[0x0b]	84611	1		T3	1		T4	503		T6	453
valid_sources[0x0c]	83122	1		T1	2		T3	1		T4	431
valid_sources[0x0d]	84008	1		T3	2		T4	458		T19	1
valid_sources[0x0e]	259670	1		T1	2		T3	3		T4	499
valid_sources[0x0f]	84106	1		T1	2		T3	3		T4	433
valid_sources[0x10]	133208	1		T1	2		T3	1		T4	463
valid_sources[0x11]	84642	1		T1	4		T3	1		T4	532
valid_sources[0x12]	84068	1		T1	4		T3	1		T4	494
valid_sources[0x13]	238541	1		T1	1		T3	3		T4	440
valid_sources[0x14]	119465	1		T1	2		T3	1		T4	566
valid_sources[0x15]	165119	1		T3	1		T4	470		T6	434
valid_sources[0x16]	83357	1		T1	1		T3	2		T4	514
valid_sources[0x17]	85202	1		T1	8		T3	3		T4	406
valid_sources[0x18]	118117	1		T1	4		T3	2		T4	516
valid_sources[0x19]	83954	1		T1	2		T3	2		T4	498
valid_sources[0x1a]	84106	1		T1	9		T4	499		T6	483
valid_sources[0x1b]	82860	1		T1	5		T3	2		T4	472
valid_sources[0x1c]	82712	1		T1	1		T3	1		T4	465
valid_sources[0x1d]	83601	1		T1	9		T3	4		T4	503
valid_sources[0x1e]	108063	1		T1	4		T3	3		T4	470
valid_sources[0x1f]	86985	1		T3	3		T4	482		T6	434
valid_sources[0x20]	86533	1		T1	1		T4	496		T6	466
valid_sources[0x21]	82941	1		T1	7		T3	2		T4	455
valid_sources[0x22]	84541	1		T1	21		T3	1		T4	412
valid_sources[0x23]	83496	1		T1	10		T4	484		T21	1
valid_sources[0x24]	83064	1		T1	6		T3	3		T4	519
valid_sources[0x25]	116737	1		T1	7		T4	531		T6	460
valid_sources[0x26]	248719	1		T1	9		T3	4		T4	474
valid_sources[0x27]	84987	1		T1	2		T3	2		T4	455
valid_sources[0x28]	85575	1		T3	1		T4	480		T17	218
valid_sources[0x29]	83805	1		T1	3		T3	1		T4	509
valid_sources[0x2a]	124512	1		T1	1		T3	2		T4	482
valid_sources[0x2b]	85100	1		T1	7		T3	3		T4	507
valid_sources[0x2c]	133301	1		T1	5		T4	474		T6	461
valid_sources[0x2d]	87995	1		T1	5		T3	1		T4	443
valid_sources[0x2e]	84172	1		T1	2		T3	4		T4	430
valid_sources[0x2f]	109015	1		T1	4		T3	3		T4	470
valid_sources[0x30]	88227	1		T1	3		T3	1		T4	470
valid_sources[0x31]	270606	1		T1	8		T3	1		T4	425
valid_sources[0x32]	165920	1		T1	2		T3	2		T4	458
valid_sources[0x33]	82831	1		T1	7		T3	4		T4	454
valid_sources[0x34]	129576	1		T3	4		T4	512		T6	463
valid_sources[0x35]	84294	1		T1	2		T4	454		T6	434
valid_sources[0x36]	132696	1		T1	2		T3	3		T4	464
valid_sources[0x37]	120002	1		T1	2		T3	2		T4	437
valid_sources[0x38]	86067	1		T1	6		T4	483		T6	455
valid_sources[0x39]	84482	1		T1	1		T3	2		T4	466
valid_sources[0x3a]	86797	1		T1	10		T3	2		T4	496
valid_sources[0x3b]	106750	1		T1	1		T3	1		T4	482
valid_sources[0x3c]	253662	1		T1	4		T3	3		T4	455
valid_sources[0x3d]	85022	1		T1	20		T3	2		T4	480
valid_sources[0x3e]	259836	1		T1	1		T4	525		T6	446
valid_sources[0x3f]	85547	1		T4	475		T6	419		T76	389
valid_sources[0x40]	110270	1		T3	2		T4	485		T6	449
valid_sources[0x41]	108736	1		T1	2		T3	3		T4	484
valid_sources[0x42]	87842	1		T1	10		T3	2		T4	472
valid_sources[0x43]	96393	1		T1	12		T3	6		T4	503
valid_sources[0x44]	83644	1		T1	9		T3	1		T4	486
valid_sources[0x45]	83767	1		T1	3		T3	4		T4	478
valid_sources[0x46]	84468	1		T1	9		T4	447		T6	459
valid_sources[0x47]	109514	1		T1	7		T3	3		T4	452
valid_sources[0x48]	82527	1		T3	1		T4	443		T6	418
valid_sources[0x49]	83346	1		T1	4		T3	6		T4	411
valid_sources[0x4a]	85613	1		T1	6		T3	1		T4	438
valid_sources[0x4b]	83540	1		T3	1		T4	482		T6	435
valid_sources[0x4c]	83861	1		T1	6		T4	504		T6	430
valid_sources[0x4d]	83184	1		T1	5		T3	1		T4	415
valid_sources[0x4e]	83116	1		T1	2		T3	3		T4	487
valid_sources[0x4f]	86163	1		T3	5		T4	549		T7	9
valid_sources[0x50]	85037	1		T1	2		T3	3		T4	511
valid_sources[0x51]	84904	1		T1	4		T4	482		T6	457
valid_sources[0x52]	86109	1		T3	2		T4	461		T6	490
valid_sources[0x53]	82789	1		T1	2		T3	4		T4	512
valid_sources[0x54]	85525	1		T1	3		T3	5		T4	468
valid_sources[0x55]	84500	1		T1	4		T3	2		T4	531
valid_sources[0x56]	85307	1		T1	8		T3	2		T4	486
valid_sources[0x57]	84111	1		T1	2		T3	1		T4	481
valid_sources[0x58]	83156	1		T1	10		T3	2		T4	479
valid_sources[0x59]	83319	1		T1	4		T3	3		T4	470
valid_sources[0x5a]	82819	1		T1	6		T4	506		T6	490
valid_sources[0x5b]	344458	1		T1	5		T4	505		T7	14
valid_sources[0x5c]	89881	1		T1	1		T3	3		T4	464
valid_sources[0x5d]	84022	1		T1	4		T3	2		T4	511
valid_sources[0x5e]	84648	1		T1	4		T4	493		T6	418
valid_sources[0x5f]	186965	1		T1	4		T3	2		T4	451
valid_sources[0x60]	83799	1		T1	3		T3	2		T4	487
valid_sources[0x61]	248601	1		T1	10		T3	1		T4	435
valid_sources[0x62]	139228	1		T3	2		T4	459		T6	454
valid_sources[0x63]	84226	1		T1	5		T3	2		T4	425
valid_sources[0x64]	83557	1		T1	2		T3	3		T4	432
valid_sources[0x65]	109679	1		T1	1		T3	4		T4	454
valid_sources[0x66]	84195	1		T1	4		T3	2		T4	449
valid_sources[0x67]	129164	1		T1	4		T3	3		T4	506
valid_sources[0x68]	84713	1		T1	5		T3	2		T4	419
valid_sources[0x69]	207405	1		T1	13		T3	1		T4	452
valid_sources[0x6a]	83817	1		T1	2		T3	2		T4	485
valid_sources[0x6b]	573226	1		T1	1		T4	478		T7	8
valid_sources[0x6c]	249113	1		T1	8		T3	1		T4	508
valid_sources[0x6d]	140329	1		T1	13		T4	498		T6	439
valid_sources[0x6e]	136070	1		T1	6		T3	2		T4	519
valid_sources[0x6f]	136833	1		T1	2		T3	2		T4	481
valid_sources[0x70]	83126	1		T1	6		T3	3		T4	455
valid_sources[0x71]	83443	1		T1	8		T3	2		T4	488
valid_sources[0x72]	86838	1		T1	2		T4	453		T19	1
valid_sources[0x73]	85419	1		T1	6		T3	3		T4	448
valid_sources[0x74]	82376	1		T1	13		T3	3		T4	499
valid_sources[0x75]	130855	1		T1	2		T3	1		T4	484
valid_sources[0x76]	83011	1		T1	8		T3	2		T4	450
valid_sources[0x77]	84496	1		T4	454		T6	447		T76	324
valid_sources[0x78]	86361	1		T1	6		T3	2		T4	472
valid_sources[0x79]	83414	1		T1	2		T3	1		T4	542
valid_sources[0x7a]	84097	1		T1	2		T3	2		T4	499
valid_sources[0x7b]	120371	1		T1	3		T3	7		T4	471
valid_sources[0x7c]	83513	1		T1	1		T3	1		T4	504
valid_sources[0x7d]	83796	1		T1	9		T3	1		T4	470
valid_sources[0x7e]	88694	1		T1	4		T3	1		T4	543
valid_sources[0x7f]	212143	1		T1	3		T3	1		T4	439
valid_sources[0x80]	83706	1		T1	5		T3	4		T4	497

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14290184

1

T1

111

T2

6

T3

1

values[0x0]

all_enables

biggest_size

192409

1

T1

181

T2

2

T3

2

values[0x1]

all_enables

biggest_size

179032

1

T1

73

T2

3

T3

6