Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14356645	1		T1	781		T2	12		T3	472
full_word	14662444	1		T1	365		T2	11		T3	9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29018789	1		T1	1146		T2	23		T3	481
auto[TlIntgErrCmd]	95	1		T204	2		T234	4		T235	2
auto[TlIntgErrData]	115	1		T204	1		T234	9		T235	3
auto[TlIntgErrBoth]	90	1		T204	7		T234	7		T235	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28532107	1		T1	221		T2	12		T3	462
auto[1]	486982	1		T1	925		T2	11		T3	19

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14241652	1		T1	110		T2	6		T3	461
auto[TlIntgErrNone]	partial	auto[1]	114724	1		T1	671		T2	6		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	14290330	1		T1	111		T2	6		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	372083	1		T1	254		T2	5		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T234	1		T235	2		T248	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T204	2		T234	3		T248	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T248	1		T321	1		T322	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T319	1		T322	2		T323	1
auto[TlIntgErrData]	partial	auto[0]	50	1		T234	7		T235	1		T248	4
auto[TlIntgErrData]	partial	auto[1]	51	1		T204	1		T234	2		T235	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T253	1		T322	1		T324	2
auto[TlIntgErrData]	full_word	auto[1]	8	1		T251	1		T325	1		T319	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T204	2		T234	1		T235	4
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T204	4		T234	5		T248	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T204	1		T235	1		T250	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T234	1		T250	1		T317	1