Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.73	97.53	86.57	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	367226109	10380	0	0
ep_in_enable_rd_A	367226109	2255	0	0
ep_out_enable_rd_A	367226109	2278	0	0
in_iso_rd_A	367226109	2207	0	0
intr_enable_rd_A	367226109	2659	0	0
out_iso_rd_A	367226109	2522	0	0
phy_config_rd_A	367226109	1417	0	0
phy_pins_drive_rd_A	367226109	1891	0	0
rxenable_setup_rd_A	367226109	1911	0	0
set_nak_out_rd_A	367226109	1954	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	10380	0	0
T202	5348	191	0	0
T203	5675	495	0	0
T204	22772	4	0	0
T227	8706	20	0	0
T234	30838	3	0	0
T235	13284	5	0	0
T236	14404	729	0	0
T237	5503	530	0	0
T248	39518	4	0	0
T249	5503	11	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	2255	0	0
T204	22772	90	0	0
T227	8706	50	0	0
T236	14404	4	0	0
T249	5503	4	0	0
T253	42030	224	0	0
T270	19564	166	0	0
T274	3230	51	0	0
T283	13733	91	0	0
T284	3617	2	0	0
T300	7664	69	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	2278	0	0
T204	22772	200	0	0
T227	8706	86	0	0
T236	14404	3	0	0
T249	5503	13	0	0
T253	42030	309	0	0
T270	19564	218	0	0
T274	3230	3	0	0
T283	13733	81	0	0
T284	3617	30	0	0
T300	7664	22	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	2207	0	0
T204	22772	126	0	0
T227	8706	14	0	0
T249	5503	3	0	0
T253	42030	377	0	0
T270	19564	211	0	0
T274	3230	12	0	0
T283	13733	93	0	0
T284	3617	31	0	0
T300	7664	47	0	0
T301	6943	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	2659	0	0
T202	5348	3	0	0
T204	22772	113	0	0
T211	4163	17	0	0
T212	2599	30	0	0
T213	1634	7	0	0
T227	8706	97	0	0
T270	19564	186	0	0
T283	13733	51	0	0
T302	1767	12	0	0
T303	2542	18	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	2522	0	0
T204	22772	116	0	0
T227	8706	74	0	0
T236	14404	5	0	0
T249	5503	27	0	0
T253	42030	250	0	0
T270	19564	193	0	0
T274	3230	48	0	0
T283	13733	35	0	0
T284	3617	44	0	0
T300	7664	37	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	1417	0	0
T204	22772	97	0	0
T227	8706	22	0	0
T249	5503	14	0	0
T253	42030	164	0	0
T270	19564	210	0	0
T274	3230	5	0	0
T283	13733	38	0	0
T284	3617	5	0	0
T300	7664	15	0	0
T301	6943	25	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	1891	0	0
T204	22772	153	0	0
T227	8706	59	0	0
T236	14404	4	0	0
T253	42030	197	0	0
T270	19564	193	0	0
T274	3230	49	0	0
T283	13733	45	0	0
T284	3617	9	0	0
T300	7664	27	0	0
T301	6943	5	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	1911	0	0
T204	22772	102	0	0
T227	8706	11	0	0
T249	5503	15	0	0
T253	42030	254	0	0
T270	19564	171	0	0
T274	3230	6	0	0
T283	13733	20	0	0
T284	3617	10	0	0
T300	7664	24	0	0
T301	6943	1	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367226109	1954	0	0
T204	22772	112	0	0
T227	8706	54	0	0
T249	5503	3	0	0
T253	42030	142	0	0
T270	19564	200	0	0
T274	3230	30	0	0
T283	13733	43	0	0
T284	3617	5	0	0
T300	7664	53	0	0
T301	6943	15	0	0