Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_7
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T20,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_7
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T20,T6 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T20,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_8
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T27,T62 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_8
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T27,T62 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T20,T27,T62 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_9
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T20,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_9
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T20,T27 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T20,T27 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_10
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T6,T26 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_10
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T6,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T20,T6,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_11
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T27,T62 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_11
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T27,T62 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T20,T27,T62 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T80,T116,T117 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T80,T116,T117 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T80,T116,T117 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T116,T117 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T116,T117 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T26,T116,T117 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_2
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T116,T117 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_2
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T116,T117 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T6,T116,T117 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_3
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T27,T116 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_3
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T27,T116 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T6,T27,T116 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T76,T116 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T76,T116 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T26,T76,T116 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T80,T116 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T80,T116 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T80,T116 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_6
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_6
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_7
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T116 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_7
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T6,T116 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T6,T116 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_8
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T82,T81,T116 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_8
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T82,T81,T116 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T82,T81,T116 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_9
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_9
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T160,T116 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_9
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T160,T116 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T160,T116 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_10
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_10
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T26,T74 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_10
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T26,T74 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T6,T26,T74 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_11
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_11
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T116,T117,T89 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_11
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T116,T117,T89 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T116,T117,T89 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_0_buffer_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_0_buffer_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T80,T152 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_0_buffer_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T80,T152 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T80,T152 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_0_size_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_0_size_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T80,T152 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_0_size_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T80,T152 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T80,T152 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_0_sending_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_0_sending_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_0_sending_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_0_pend_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_0_pend_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_0_pend_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_0_rdy_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_0_rdy_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_0_rdy_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_1_buffer_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_1_buffer_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T17,T26 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_1_buffer_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T17,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T17,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_1_size_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_1_size_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T17,T26 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_1_size_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T17,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T17,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_1_sending_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_1_sending_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_1_sending_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_1_pend_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_1_pend_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_1_pend_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_1_rdy_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_1_rdy_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_1_rdy_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_2_buffer_2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_2_buffer_2
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T7,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_2_buffer_2
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T7,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_2_size_2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_2_size_2
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T7,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_2_size_2
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T7,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_2_sending_2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_2_sending_2
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_2_sending_2
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_2_pend_2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_2_pend_2
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_2_pend_2
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_2_rdy_2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_2_rdy_2
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_2_rdy_2
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_3_buffer_3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_3_buffer_3
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T17,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_3_buffer_3
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T17,T6 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T17,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_3_size_3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_3_size_3
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T17,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_3_size_3
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T17,T6 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T17,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_3_sending_3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_3_sending_3
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_3_sending_3
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_3_pend_3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_3_pend_3
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_3_pend_3
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_3_rdy_3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_3_rdy_3
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_3_rdy_3
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_4_buffer_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_4_buffer_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T5,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_4_buffer_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T5,T17 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T5,T17 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_4_size_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_4_size_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T5,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_4_size_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T5,T17 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T5,T17 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_4_sending_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_4_sending_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_4_sending_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_4_pend_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_4_pend_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_4_pend_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_4_rdy_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_4_rdy_4
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_4_rdy_4
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_5_buffer_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_5_buffer_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_5_buffer_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T5,T17 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T5,T17 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_5_size_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_5_size_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_5_size_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T5,T17 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T5,T17 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_5_sending_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_5_sending_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_5_sending_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_5_pend_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_5_pend_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_5_pend_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_5_rdy_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_5_rdy_5
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_5_rdy_5
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_6_buffer_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_6_buffer_6
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_6_buffer_6
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T17 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T5,T17 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_6_size_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_6_size_6
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_6_size_6
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T17 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T5,T17 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_6_sending_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_6_sending_6
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_6_sending_6
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_6_pend_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_6_pend_6
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_6_pend_6
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_6_rdy_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_6_rdy_6
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_6_rdy_6
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_7_buffer_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_7_buffer_7
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T17,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_7_buffer_7
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T17,T6 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T17,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_7_size_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_7_size_7
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T17,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_7_size_7
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T17,T6 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T17,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_7_sending_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_7_sending_7
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_7_sending_7
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_7_pend_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_7_pend_7
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_7_pend_7
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_7_rdy_7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_7_rdy_7
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_7_rdy_7
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_8_buffer_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_8_buffer_8
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T6,T26 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_8_buffer_8
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T6,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T6,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_configin_8_size_8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_configin_8_size_8
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T6,T26 |
Branch Coverage for Instance : tb.dut.u_reg.u_configin_8_size_8
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T6,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T6,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |