Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14890898	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15213146	1		T1	120		T2	51020		T3	20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29614278	1		T1	79		T2	102053		T3	17
values[0x0]	244113	1		T1	34		T2	148		T3	5
values[0x1]	245653	1		T1	23		T2	148		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11869509	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18234535	1		T1	124		T2	61525		T3	21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	84124	1		T29	2		T4	381		T5	130
valid_sources[0x01]	82405	1		T1	2		T4	397		T81	3
valid_sources[0x02]	154642	1		T29	5		T4	385		T5	119
valid_sources[0x03]	84278	1		T1	2		T29	2		T4	412
valid_sources[0x04]	84066	1		T4	372		T18	2		T5	115
valid_sources[0x05]	84891	1		T1	1		T29	2		T4	403
valid_sources[0x06]	430808	1		T29	1		T4	385		T81	6
valid_sources[0x07]	85810	1		T1	6		T29	3		T4	374
valid_sources[0x08]	84551	1		T4	392		T6	1		T5	111
valid_sources[0x09]	83254	1		T29	1		T4	376		T18	4
valid_sources[0x0a]	86152	1		T4	414		T81	3		T51	1
valid_sources[0x0b]	84290	1		T1	6		T4	358		T81	1
valid_sources[0x0c]	83649	1		T1	1		T4	362		T5	130
valid_sources[0x0d]	178893	1		T4	376		T81	3		T5	96
valid_sources[0x0e]	111345	1		T1	2		T29	2		T4	351
valid_sources[0x0f]	83430	1		T3	1		T29	2		T4	378
valid_sources[0x10]	86578	1		T4	374		T81	6		T5	123
valid_sources[0x11]	85043	1		T4	366		T81	12		T18	6
valid_sources[0x12]	85654	1		T4	368		T5	75		T7	3
valid_sources[0x13]	85340	1		T3	1		T4	366		T81	1
valid_sources[0x14]	85841	1		T1	1		T4	385		T81	1
valid_sources[0x15]	84278	1		T4	402		T81	1		T5	118
valid_sources[0x16]	283706	1		T4	404		T81	1		T5	97
valid_sources[0x17]	83647	1		T29	1		T4	347		T18	1
valid_sources[0x18]	85188	1		T4	338		T81	7		T6	2
valid_sources[0x19]	83900	1		T4	368		T18	1		T5	83
valid_sources[0x1a]	83737	1		T4	362		T18	4		T5	110
valid_sources[0x1b]	83922	1		T4	392		T81	7		T5	95
valid_sources[0x1c]	208774	1		T29	1		T4	417		T19	1
valid_sources[0x1d]	83301	1		T3	1		T4	393		T81	4
valid_sources[0x1e]	84132	1		T29	2		T4	359		T5	116
valid_sources[0x1f]	83538	1		T4	397		T81	1		T5	113
valid_sources[0x20]	82455	1		T29	1		T4	384		T30	1
valid_sources[0x21]	89935	1		T1	8		T4	355		T31	6
valid_sources[0x22]	87778	1		T29	1		T4	390		T31	2
valid_sources[0x23]	83002	1		T4	401		T81	1		T5	137
valid_sources[0x24]	85252	1		T4	359		T81	1		T5	97
valid_sources[0x25]	83067	1		T3	1		T29	2		T4	393
valid_sources[0x26]	109173	1		T4	397		T18	2		T19	1
valid_sources[0x27]	83863	1		T4	416		T32	1		T81	8
valid_sources[0x28]	83168	1		T1	1		T29	1		T4	388
valid_sources[0x29]	85947	1		T4	387		T81	6		T18	2
valid_sources[0x2a]	85983	1		T1	1		T4	343		T6	1
valid_sources[0x2b]	83090	1		T4	324		T81	3		T17	1
valid_sources[0x2c]	84756	1		T4	391		T81	3		T18	1
valid_sources[0x2d]	82747	1		T3	1		T4	423		T6	1
valid_sources[0x2e]	549199	1		T29	3		T4	371		T81	7
valid_sources[0x2f]	302965	1		T29	2		T4	389		T81	4
valid_sources[0x30]	85424	1		T4	388		T81	3		T6	2
valid_sources[0x31]	82058	1		T29	1		T4	435		T81	5
valid_sources[0x32]	101985	1		T4	390		T31	1		T81	12
valid_sources[0x33]	83407	1		T4	408		T81	7		T18	4
valid_sources[0x34]	261111	1		T2	102349		T4	438		T81	2
valid_sources[0x35]	87968	1		T1	3		T4	416		T81	5
valid_sources[0x36]	83419	1		T1	1		T29	1		T4	428
valid_sources[0x37]	83987	1		T4	386		T81	1		T6	3
valid_sources[0x38]	397396	1		T29	1		T4	368		T81	5
valid_sources[0x39]	85294	1		T4	326		T81	4		T6	2
valid_sources[0x3a]	84025	1		T1	3		T29	2		T4	364
valid_sources[0x3b]	84404	1		T29	1		T4	368		T30	1
valid_sources[0x3c]	82959	1		T29	1		T4	447		T81	2
valid_sources[0x3d]	82667	1		T1	4		T28	5		T29	1
valid_sources[0x3e]	85151	1		T29	4		T4	378		T5	124
valid_sources[0x3f]	84252	1		T4	415		T6	2		T5	152
valid_sources[0x40]	82349	1		T29	1		T4	365		T31	2
valid_sources[0x41]	233427	1		T29	2		T4	401		T81	4
valid_sources[0x42]	83285	1		T4	358		T5	95		T7	5
valid_sources[0x43]	82741	1		T4	365		T81	4		T6	2
valid_sources[0x44]	83383	1		T1	2		T4	371		T81	3
valid_sources[0x45]	83995	1		T4	396		T19	1		T51	3
valid_sources[0x46]	83034	1		T4	390		T81	1		T5	97
valid_sources[0x47]	83619	1		T29	3		T4	357		T81	1
valid_sources[0x48]	257785	1		T4	372		T81	6		T51	1
valid_sources[0x49]	314075	1		T4	417		T81	12		T5	88
valid_sources[0x4a]	113621	1		T1	5		T28	3		T29	2
valid_sources[0x4b]	83609	1		T4	363		T81	1		T18	3
valid_sources[0x4c]	83999	1		T29	2		T4	397		T6	2
valid_sources[0x4d]	83838	1		T29	3		T4	389		T81	3
valid_sources[0x4e]	82235	1		T29	1		T4	367		T32	1
valid_sources[0x4f]	84378	1		T4	425		T81	1		T18	2
valid_sources[0x50]	118284	1		T1	2		T29	4		T4	402
valid_sources[0x51]	83579	1		T29	1		T4	348		T81	10
valid_sources[0x52]	83049	1		T29	2		T4	372		T18	3
valid_sources[0x53]	83310	1		T1	1		T4	364		T81	14
valid_sources[0x54]	82916	1		T1	1		T29	2		T4	396
valid_sources[0x55]	84528	1		T29	1		T4	375		T81	10
valid_sources[0x56]	83231	1		T4	341		T81	1		T6	1
valid_sources[0x57]	83186	1		T1	3		T4	367		T81	13
valid_sources[0x58]	83475	1		T1	5		T29	1		T4	399
valid_sources[0x59]	83405	1		T29	1		T4	396		T18	1
valid_sources[0x5a]	133513	1		T29	1		T4	412		T81	17
valid_sources[0x5b]	89651	1		T4	331		T81	3		T18	4
valid_sources[0x5c]	83037	1		T29	1		T4	379		T6	3
valid_sources[0x5d]	193767	1		T4	406		T81	1		T6	2
valid_sources[0x5e]	81525	1		T4	370		T81	3		T18	2
valid_sources[0x5f]	234589	1		T4	435		T32	1		T81	3
valid_sources[0x60]	83163	1		T29	2		T4	400		T30	5
valid_sources[0x61]	84104	1		T4	423		T81	9		T18	5
valid_sources[0x62]	83586	1		T1	1		T4	388		T81	3
valid_sources[0x63]	82564	1		T4	375		T81	6		T5	157
valid_sources[0x64]	84152	1		T4	375		T81	6		T5	109
valid_sources[0x65]	83639	1		T1	2		T29	4		T4	374
valid_sources[0x66]	117496	1		T3	2		T29	1		T4	380
valid_sources[0x67]	83065	1		T4	385		T81	10		T19	1
valid_sources[0x68]	84303	1		T1	2		T29	1		T4	365
valid_sources[0x69]	319340	1		T1	2		T29	1		T4	375
valid_sources[0x6a]	175434	1		T29	4		T4	383		T6	1
valid_sources[0x6b]	83572	1		T3	1		T4	407		T31	1
valid_sources[0x6c]	85127	1		T29	1		T4	351		T81	1
valid_sources[0x6d]	82652	1		T29	2		T4	370		T81	3
valid_sources[0x6e]	83954	1		T29	3		T4	375		T81	3
valid_sources[0x6f]	85297	1		T3	1		T4	346		T81	12
valid_sources[0x70]	85560	1		T29	1		T4	369		T81	2
valid_sources[0x71]	82435	1		T4	373		T32	1		T81	4
valid_sources[0x72]	117431	1		T29	1		T4	375		T81	1
valid_sources[0x73]	82970	1		T4	388		T6	1		T18	1
valid_sources[0x74]	84699	1		T1	1		T29	2		T4	400
valid_sources[0x75]	111965	1		T1	1		T29	3		T4	407
valid_sources[0x76]	176028	1		T29	1		T4	353		T81	6
valid_sources[0x77]	84742	1		T1	1		T4	358		T81	16
valid_sources[0x78]	83502	1		T1	3		T4	376		T81	4
valid_sources[0x79]	83877	1		T4	392		T81	3		T5	137
valid_sources[0x7a]	83756	1		T29	1		T4	417		T81	2
valid_sources[0x7b]	87762	1		T1	1		T4	405		T81	4
valid_sources[0x7c]	84921	1		T4	375		T81	1		T51	1
valid_sources[0x7d]	83486	1		T4	361		T5	122		T43	26
valid_sources[0x7e]	84084	1		T29	2		T4	357		T5	100
valid_sources[0x7f]	125187	1		T4	412		T81	1		T6	2
valid_sources[0x80]	85055	1		T29	1		T4	383		T81	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14831186

1

T1

77

T2

50812

T3

15

values[0x0]

all_enables

biggest_size

197290

1

T1

27

T2

106

T3

4

values[0x1]

all_enables

biggest_size

184670

1

T1

16

T2

102

T3

1