Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14905192	1		T1	16		T2	51329		T3	6
full_word	15214184	1		T1	120		T2	51020		T3	20

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30119096	1		T1	136		T2	102349		T3	26
auto[TlIntgErrCmd]	88	1		T223	4		T224	7		T230	6
auto[TlIntgErrData]	93	1		T223	4		T224	5		T230	2
auto[TlIntgErrBoth]	99	1		T223	2		T224	8		T230	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29616093	1		T1	79		T2	102053		T3	17
auto[1]	503283	1		T1	57		T2	296		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14784582	1		T1	2		T2	51241		T3	2
auto[TlIntgErrNone]	partial	auto[1]	120350	1		T1	14		T2	88		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	14831379	1		T1	77		T2	50812		T3	15
auto[TlIntgErrNone]	full_word	auto[1]	382785	1		T1	43		T2	208		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T223	1		T224	4		T230	2
auto[TlIntgErrCmd]	partial	auto[1]	39	1		T223	3		T224	3		T230	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T230	1		T282	1		T283	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T230	1		T284	1		T285	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T223	1		T224	4		T280	2
auto[TlIntgErrData]	partial	auto[1]	38	1		T223	2		T224	1		T230	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T223	1		T280	2		T286	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T287	1		T286	1		T288	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T223	1		T224	3		T280	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T223	1		T224	4		T230	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T224	1		T289	1		T287	1