Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13669883	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	13955148	1		T1	12		T2	5		T3	80061

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27160390	1		T1	9		T2	2		T3	159317
values[0x0]	232219	1		T1	6		T2	4		T3	245
values[0x1]	232422	1		T1	3		T2	3		T3	264

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10893826	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	16731205	1		T1	14		T2	6		T3	96236

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	79922	1		T3	588		T4	700		T5	109
valid_sources[0x01]	79855	1		T3	650		T4	701		T5	121
valid_sources[0x02]	393081	1		T3	637		T4	651		T30	1
valid_sources[0x03]	81149	1		T3	651		T4	725		T5	109
valid_sources[0x04]	78856	1		T3	532		T4	714		T5	102
valid_sources[0x05]	79479	1		T3	652		T4	653		T5	88
valid_sources[0x06]	80014	1		T2	1		T3	642		T4	704
valid_sources[0x07]	80517	1		T3	615		T4	733		T5	118
valid_sources[0x08]	318243	1		T3	587		T4	666		T6	31
valid_sources[0x09]	81103	1		T3	637		T4	727		T5	104
valid_sources[0x0a]	81034	1		T3	600		T4	689		T5	103
valid_sources[0x0b]	78629	1		T3	641		T4	692		T5	117
valid_sources[0x0c]	79920	1		T3	658		T4	676		T5	126
valid_sources[0x0d]	97405	1		T3	704		T4	656		T5	107
valid_sources[0x0e]	80687	1		T3	583		T4	694		T5	130
valid_sources[0x0f]	79540	1		T3	587		T4	682		T5	106
valid_sources[0x10]	80234	1		T3	594		T4	701		T5	120
valid_sources[0x11]	310704	1		T3	663		T4	704		T5	120
valid_sources[0x12]	80717	1		T3	570		T4	718		T5	103
valid_sources[0x13]	194144	1		T3	640		T4	666		T30	1
valid_sources[0x14]	116052	1		T3	691		T4	673		T6	38
valid_sources[0x15]	79976	1		T3	598		T4	681		T6	35
valid_sources[0x16]	255184	1		T2	2		T3	663		T4	651
valid_sources[0x17]	78551	1		T3	642		T4	644		T5	95
valid_sources[0x18]	79625	1		T3	696		T4	681		T5	99
valid_sources[0x19]	84258	1		T3	550		T4	684		T29	3
valid_sources[0x1a]	79418	1		T3	647		T4	680		T30	2
valid_sources[0x1b]	79667	1		T2	1		T3	616		T4	708
valid_sources[0x1c]	78809	1		T3	573		T4	719		T29	1
valid_sources[0x1d]	79493	1		T3	656		T4	701		T26	1
valid_sources[0x1e]	154161	1		T3	589		T4	706		T6	5
valid_sources[0x1f]	81428	1		T3	587		T4	730		T5	108
valid_sources[0x20]	78965	1		T3	609		T4	620		T29	4
valid_sources[0x21]	79347	1		T3	657		T4	660		T5	116
valid_sources[0x22]	107093	1		T3	652		T4	654		T5	107
valid_sources[0x23]	160209	1		T3	615		T4	767		T5	89
valid_sources[0x24]	79937	1		T3	707		T4	680		T30	1
valid_sources[0x25]	79516	1		T3	594		T4	661		T5	121
valid_sources[0x26]	81265	1		T3	609		T4	691		T5	128
valid_sources[0x27]	132777	1		T3	609		T4	713		T5	112
valid_sources[0x28]	154892	1		T3	619		T4	729		T29	2
valid_sources[0x29]	86113	1		T3	590		T4	639		T5	109
valid_sources[0x2a]	144985	1		T3	602		T4	667		T5	127
valid_sources[0x2b]	81323	1		T3	603		T4	675		T5	108
valid_sources[0x2c]	78458	1		T3	656		T4	652		T5	97
valid_sources[0x2d]	364637	1		T3	663		T4	704		T5	109
valid_sources[0x2e]	79160	1		T3	590		T4	703		T5	123
valid_sources[0x2f]	84175	1		T3	651		T4	681		T29	3
valid_sources[0x30]	151112	1		T3	678		T4	688		T5	103
valid_sources[0x31]	252830	1		T3	589		T4	678		T5	130
valid_sources[0x32]	79246	1		T3	642		T4	679		T30	1
valid_sources[0x33]	80456	1		T3	642		T4	733		T5	127
valid_sources[0x34]	80817	1		T3	667		T4	651		T5	96
valid_sources[0x35]	81685	1		T3	671		T4	710		T5	113
valid_sources[0x36]	79223	1		T3	672		T4	723		T5	108
valid_sources[0x37]	79027	1		T3	605		T4	710		T5	100
valid_sources[0x38]	131292	1		T3	631		T4	691		T5	93
valid_sources[0x39]	79933	1		T3	603		T4	697		T5	116
valid_sources[0x3a]	80043	1		T1	1		T3	643		T4	745
valid_sources[0x3b]	79147	1		T3	599		T4	684		T5	128
valid_sources[0x3c]	82862	1		T3	612		T4	708		T5	117
valid_sources[0x3d]	84758	1		T3	554		T4	710		T5	102
valid_sources[0x3e]	82265	1		T3	550		T4	640		T5	107
valid_sources[0x3f]	81257	1		T3	617		T4	762		T5	121
valid_sources[0x40]	79918	1		T3	554		T4	707		T5	103
valid_sources[0x41]	81923	1		T3	598		T4	737		T5	108
valid_sources[0x42]	254098	1		T3	684		T4	685		T29	1
valid_sources[0x43]	80590	1		T3	611		T4	672		T5	128
valid_sources[0x44]	79872	1		T3	644		T4	736		T5	111
valid_sources[0x45]	80065	1		T3	603		T4	726		T5	104
valid_sources[0x46]	169734	1		T3	627		T4	660		T5	117
valid_sources[0x47]	118076	1		T3	636		T4	654		T5	127
valid_sources[0x48]	80037	1		T3	576		T4	706		T26	1
valid_sources[0x49]	79949	1		T3	649		T4	689		T29	3
valid_sources[0x4a]	172436	1		T3	593		T4	703		T5	123
valid_sources[0x4b]	118421	1		T3	676		T4	672		T5	142
valid_sources[0x4c]	79858	1		T3	584		T4	650		T5	96
valid_sources[0x4d]	79341	1		T3	593		T4	667		T5	126
valid_sources[0x4e]	81324	1		T3	624		T4	702		T5	113
valid_sources[0x4f]	185963	1		T3	670		T4	721		T5	99
valid_sources[0x50]	80459	1		T3	648		T4	699		T30	1
valid_sources[0x51]	80471	1		T3	576		T4	627		T5	123
valid_sources[0x52]	111838	1		T3	632		T4	705		T5	122
valid_sources[0x53]	79110	1		T3	571		T4	689		T5	120
valid_sources[0x54]	81908	1		T3	629		T4	705		T5	126
valid_sources[0x55]	79411	1		T3	576		T4	669		T5	118
valid_sources[0x56]	192825	1		T3	671		T4	704		T5	127
valid_sources[0x57]	80608	1		T2	1		T3	633		T4	698
valid_sources[0x58]	115569	1		T3	569		T4	697		T5	128
valid_sources[0x59]	79886	1		T3	688		T4	682		T29	1
valid_sources[0x5a]	197321	1		T3	677		T4	688		T5	112
valid_sources[0x5b]	79999	1		T2	1		T3	565		T4	705
valid_sources[0x5c]	159680	1		T3	637		T4	695		T5	131
valid_sources[0x5d]	79359	1		T3	636		T4	750		T5	122
valid_sources[0x5e]	80429	1		T3	678		T4	684		T5	133
valid_sources[0x5f]	79569	1		T3	561		T4	680		T5	112
valid_sources[0x60]	79999	1		T3	641		T4	726		T6	26
valid_sources[0x61]	467793	1		T3	658		T4	727		T5	108
valid_sources[0x62]	110475	1		T3	627		T4	651		T5	110
valid_sources[0x63]	106314	1		T3	640		T4	663		T5	99
valid_sources[0x64]	227634	1		T2	1		T3	636		T4	650
valid_sources[0x65]	78198	1		T3	583		T4	710		T26	1
valid_sources[0x66]	80870	1		T3	660		T4	700		T5	95
valid_sources[0x67]	79874	1		T3	637		T4	714		T5	140
valid_sources[0x68]	79521	1		T3	608		T4	698		T5	121
valid_sources[0x69]	80260	1		T3	685		T4	646		T5	119
valid_sources[0x6a]	109305	1		T1	15		T3	585		T4	720
valid_sources[0x6b]	119358	1		T3	652		T4	724		T5	122
valid_sources[0x6c]	79716	1		T3	599		T4	613		T5	125
valid_sources[0x6d]	79844	1		T3	558		T4	697		T5	116
valid_sources[0x6e]	81755	1		T3	600		T4	692		T5	121
valid_sources[0x6f]	79839	1		T3	626		T4	715		T30	1
valid_sources[0x70]	219628	1		T3	595		T4	690		T5	89
valid_sources[0x71]	77892	1		T3	610		T4	719		T5	104
valid_sources[0x72]	112996	1		T3	598		T4	720		T5	127
valid_sources[0x73]	83937	1		T3	680		T4	670		T5	115
valid_sources[0x74]	79514	1		T3	655		T4	692		T5	102
valid_sources[0x75]	82330	1		T3	609		T4	729		T5	105
valid_sources[0x76]	126840	1		T3	602		T4	659		T5	126
valid_sources[0x77]	78881	1		T3	690		T4	693		T5	117
valid_sources[0x78]	79347	1		T3	585		T4	691		T5	121
valid_sources[0x79]	80046	1		T3	607		T4	697		T5	126
valid_sources[0x7a]	78008	1		T3	640		T4	655		T5	124
valid_sources[0x7b]	79149	1		T3	728		T4	684		T5	105
valid_sources[0x7c]	137847	1		T3	580		T4	680		T5	101
valid_sources[0x7d]	79239	1		T3	615		T4	692		T5	120
valid_sources[0x7e]	79468	1		T3	601		T4	690		T5	104
valid_sources[0x7f]	80149	1		T3	624		T4	697		T5	89
valid_sources[0x80]	105465	1		T3	592		T4	664		T5	126

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13594455

1

T1

6

T2

1

T3

79701

values[0x0]

all_enables

biggest_size

187220

1

T1

4

T2

3

T3

176

values[0x1]

all_enables

biggest_size

173473

1

T1

2

T2

1

T3

184