Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	13682247	1		T1	6		T2	4		T3	79765
full_word	13955936	1		T1	12		T2	5		T3	80061

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	27637903	1		T1	18		T2	9		T3	159826
auto[TlIntgErrCmd]	91	1		T203	7		T204	2		T231	2
auto[TlIntgErrData]	109	1		T203	6		T204	5		T231	5
auto[TlIntgErrBoth]	80	1		T203	7		T204	3		T231	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27161872	1		T1	9		T2	2		T3	159317
auto[1]	476311	1		T1	9		T2	7		T3	509

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	13567167	1		T1	3		T2	1		T3	79616
auto[TlIntgErrNone]	partial	auto[1]	114830	1		T1	3		T2	3		T3	149
auto[TlIntgErrNone]	full_word	auto[0]	13594580	1		T1	6		T2	1		T3	79701
auto[TlIntgErrNone]	full_word	auto[1]	361326	1		T1	6		T2	4		T3	360
auto[TlIntgErrCmd]	partial	auto[0]	28	1		T203	4		T251	3		T247	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T203	3		T204	2		T251	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T231	1		T251	1		T246	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T231	1		T251	1		T314	1
auto[TlIntgErrData]	partial	auto[0]	53	1		T203	1		T204	3		T231	2
auto[TlIntgErrData]	partial	auto[1]	45	1		T203	4		T204	1		T231	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T251	1		T289	1		T317	2
auto[TlIntgErrData]	full_word	auto[1]	6	1		T203	1		T204	1		T231	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T203	3		T204	1		T231	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1		T203	4		T204	2		T231	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T246	1		T250	1		T314	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T246	1		T250	1		T316	1