Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	365660346	10636	0	0
ep_in_enable_rd_A	365660346	3989	0	0
ep_out_enable_rd_A	365660346	3933	0	0
in_iso_rd_A	365660346	3057	0	0
intr_enable_rd_A	365660346	4212	0	0
out_iso_rd_A	365660346	3277	0	0
phy_config_rd_A	365660346	2397	0	0
phy_pins_drive_rd_A	365660346	2793	0	0
rxenable_setup_rd_A	365660346	3627	0	0
set_nak_out_rd_A	365660346	3461	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	10636	0	0
T203	48725	6	0	0
T204	27197	2	0	0
T205	5679	307	0	0
T226	7323	13	0	0
T227	7852	401	0	0
T231	38136	3	0	0
T234	4006	15	0	0
T246	62163	2	0	0
T247	17022	4	0	0
T251	45414	6	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	3989	0	0
T203	48725	746	0	0
T204	27197	88	0	0
T268	3926	85	0	0
T277	151476	449	0	0
T286	4702	26	0	0
T287	10897	42	0	0
T288	10379	46	0	0
T289	37144	409	0	0
T290	6163	11	0	0
T291	9906	112	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	3933	0	0
T203	48725	646	0	0
T204	27197	145	0	0
T268	3926	62	0	0
T277	151476	488	0	0
T280	5702	30	0	0
T286	4702	26	0	0
T287	10897	16	0	0
T288	10379	50	0	0
T289	37144	502	0	0
T290	6163	1	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	3057	0	0
T203	48725	386	0	0
T204	27197	163	0	0
T268	3926	48	0	0
T277	151476	431	0	0
T280	5702	8	0	0
T286	4702	32	0	0
T287	10897	21	0	0
T288	10379	38	0	0
T289	37144	276	0	0
T290	6163	26	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	4212	0	0
T203	48725	415	0	0
T204	27197	196	0	0
T210	2383	20	0	0
T211	1765	14	0	0
T268	3926	3	0	0
T280	5702	11	0	0
T292	2044	12	0	0
T293	2800	18	0	0
T294	2515	28	0	0
T295	2574	16	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	3277	0	0
T203	48725	720	0	0
T204	27197	89	0	0
T268	3926	52	0	0
T277	151476	448	0	0
T280	5702	43	0	0
T286	4702	3	0	0
T287	10897	10	0	0
T288	10379	50	0	0
T289	37144	257	0	0
T290	6163	60	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	2397	0	0
T203	48725	312	0	0
T204	27197	92	0	0
T268	3926	31	0	0
T277	151476	405	0	0
T280	5702	34	0	0
T286	4702	3	0	0
T287	10897	13	0	0
T288	10379	66	0	0
T289	37144	252	0	0
T290	6163	45	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	2793	0	0
T203	48725	390	0	0
T204	27197	83	0	0
T268	3926	51	0	0
T277	151476	375	0	0
T280	5702	25	0	0
T286	4702	6	0	0
T287	10897	26	0	0
T288	10379	39	0	0
T289	37144	379	0	0
T290	6163	35	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	3627	0	0
T203	48725	459	0	0
T204	27197	128	0	0
T236	8990	5	0	0
T268	3926	77	0	0
T277	151476	458	0	0
T280	5702	14	0	0
T286	4702	7	0	0
T287	10897	9	0	0
T288	10379	68	0	0
T289	37144	665	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	3461	0	0
T203	48725	651	0	0
T204	27197	60	0	0
T268	3926	52	0	0
T277	151476	411	0	0
T280	5702	14	0	0
T286	4702	29	0	0
T287	10897	50	0	0
T288	10379	58	0	0
T289	37144	484	0	0
T290	6163	11	0	0