Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	88.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	88.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T77
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T29

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	363733187	143307416	0	0
DepthKnown_A	363733187	363537524	0	0
RvalidKnown_A	363733187	363537524	0	0
WreadyKnown_A	363733187	363537524	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	363733187	143307416	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	143307416	0	0
T2	7694	560	0	0
T3	325909	320307	0	0
T4	362558	356939	0	0
T5	310267	304338	0	0
T6	643048	0	0	0
T18	0	568	0	0
T20	0	222671	0	0
T22	0	558	0	0
T26	9248	0	0	0
T27	10026	0	0	0
T28	51105	0	0	0
T29	9695	571	0	0
T30	9296	0	0	0
T66	0	309261	0	0
T75	0	438494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	143307416	0	0
T2	7694	560	0	0
T3	325909	320307	0	0
T4	362558	356939	0	0
T5	310267	304338	0	0
T6	643048	0	0	0
T18	0	568	0	0
T20	0	222671	0	0
T22	0	558	0	0
T26	9248	0	0	0
T27	10026	0	0	0
T28	51105	0	0	0
T29	9695	571	0	0
T30	9296	0	0	0
T66	0	309261	0	0
T75	0	438494	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T57,T58,T59
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	363733187	169196977	0	0
DepthKnown_A	363733187	363537524	0	0
RvalidKnown_A	363733187	363537524	0	0
WreadyKnown_A	363733187	363537524	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	363733187	169196977	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	169196977	0	0
T1	8835	954	0	0
T2	7694	0	0	0
T3	325909	320291	0	0
T4	362558	356923	0	0
T5	0	304268	0	0
T6	643048	2321	0	0
T26	9248	303	0	0
T27	10026	1107	0	0
T28	51105	17508	0	0
T29	9695	1009	0	0
T30	9296	1275	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	169196977	0	0
T1	8835	954	0	0
T2	7694	0	0	0
T3	325909	320291	0	0
T4	362558	356923	0	0
T5	0	304268	0	0
T6	643048	2321	0	0
T26	9248	303	0	0
T27	10026	1107	0	0
T28	51105	17508	0	0
T29	9695	1009	0	0
T30	9296	1275	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	363733187	20751402	0	0
DepthKnown_A	363733187	363537524	0	0
RvalidKnown_A	363733187	363537524	0	0
WreadyKnown_A	363733187	363537524	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	363733187	20751402	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	20751402	0	0
T1	8835	92	0	0
T2	7694	910	0	0
T3	325909	940	0	0
T4	362558	716	0	0
T6	643048	108	0	0
T26	9248	1416	0	0
T27	10026	90	0	0
T28	51105	1320	0	0
T29	9695	213	0	0
T30	9296	2299	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	20751402	0	0
T1	8835	92	0	0
T2	7694	910	0	0
T3	325909	940	0	0
T4	362558	716	0	0
T6	643048	108	0	0
T26	9248	1416	0	0
T27	10026	90	0	0
T28	51105	1320	0	0
T29	9695	213	0	0
T30	9296	2299	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365660346	27867085	0	0
DepthKnown_A	365660346	365410582	0	0
RvalidKnown_A	365660346	365410582	0	0
WreadyKnown_A	365660346	365410582	0	0
gen_passthru_fifo.paramCheckPass	2736	2736	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	27867085	0	0
T1	8835	18	0	0
T2	7694	9	0	0
T3	325909	159826	0	0
T4	362558	177361	0	0
T6	643048	343	0	0
T26	9248	12	0	0
T27	10026	24	0	0
T28	51105	297	0	0
T29	9695	39	0	0
T30	9296	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2736	2736	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365660346	38872573	0	0
DepthKnown_A	365660346	365410582	0	0
RvalidKnown_A	365660346	365410582	0	0
WreadyKnown_A	365660346	365410582	0	0
gen_passthru_fifo.paramCheckPass	2736	2736	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	38872573	0	0
T1	8835	88	0	0
T2	7694	41	0	0
T3	325909	159826	0	0
T4	362558	177361	0	0
T6	643048	343	0	0
T26	9248	12	0	0
T27	10026	24	0	0
T28	51105	1344	0	0
T29	9695	39	0	0
T30	9296	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2736	2736	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365660346	390259	0	0
DepthKnown_A	365660346	365410582	0	0
RvalidKnown_A	365660346	365410582	0	0
WreadyKnown_A	365660346	365410582	0	0
gen_passthru_fifo.paramCheckPass	2736	2736	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	390259	0	0
T1	8835	5	0	0
T2	7694	0	0	0
T3	325909	0	0	0
T4	362558	0	0	0
T6	643048	0	0	0
T17	0	15	0	0
T19	0	55	0	0
T22	0	9	0	0
T26	9248	0	0	0
T27	10026	7	0	0
T28	51105	107	0	0
T29	9695	16	0	0
T30	9296	0	0	0
T42	0	14	0	0
T52	0	25	0	0
T76	0	9661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2736	2736	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365660346	674009	0	0
DepthKnown_A	365660346	365410582	0	0
RvalidKnown_A	365660346	365410582	0	0
WreadyKnown_A	365660346	365410582	0	0
gen_passthru_fifo.paramCheckPass	2736	2736	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	674009	0	0
T1	8835	27	0	0
T2	7694	0	0	0
T3	325909	0	0	0
T4	362558	0	0	0
T6	643048	0	0	0
T17	0	68	0	0
T19	0	55	0	0
T22	0	9	0	0
T26	9248	0	0	0
T27	10026	7	0	0
T28	51105	503	0	0
T29	9695	16	0	0
T30	9296	0	0	0
T42	0	14	0	0
T52	0	25	0	0
T76	0	9661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2736	2736	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365660346	27422374	0	0
DepthKnown_A	365660346	365410582	0	0
RvalidKnown_A	365660346	365410582	0	0
WreadyKnown_A	365660346	365410582	0	0
gen_passthru_fifo.paramCheckPass	2736	2736	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	27422374	0	0
T1	8835	13	0	0
T2	7694	9	0	0
T3	325909	159826	0	0
T4	362558	177361	0	0
T6	643048	343	0	0
T26	9248	12	0	0
T27	10026	17	0	0
T28	51105	190	0	0
T29	9695	23	0	0
T30	9296	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2736	2736	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365660346	38198564	0	0
DepthKnown_A	365660346	365410582	0	0
RvalidKnown_A	365660346	365410582	0	0
WreadyKnown_A	365660346	365410582	0	0
gen_passthru_fifo.paramCheckPass	2736	2736	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	38198564	0	0
T1	8835	61	0	0
T2	7694	41	0	0
T3	325909	159826	0	0
T4	362558	177361	0	0
T6	643048	343	0	0
T26	9248	12	0	0
T27	10026	17	0	0
T28	51105	841	0	0
T29	9695	23	0	0
T30	9296	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365660346	365410582	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2736	2736	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T27,T28

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T27,T28

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T27,T28
1	1	0	Not Covered
1	1	1	Covered	T1,T27,T28

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T27,T28
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T27,T28

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T27,T28
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	363733187	621806	0	0
DepthKnown_A	363733187	363537524	0	0
RvalidKnown_A	363733187	363537524	0	0
WreadyKnown_A	363733187	363537524	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	363733187	621806	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	621806	0	0
T1	8835	27	0	0
T2	7694	0	0	0
T3	325909	0	0	0
T4	362558	0	0	0
T6	643048	0	0	0
T17	0	68	0	0
T19	0	55	0	0
T22	0	9	0	0
T26	9248	0	0	0
T27	10026	7	0	0
T28	51105	503	0	0
T29	9695	16	0	0
T30	9296	0	0	0
T42	0	14	0	0
T52	0	25	0	0
T76	0	9661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	621806	0	0
T1	8835	27	0	0
T2	7694	0	0	0
T3	325909	0	0	0
T4	362558	0	0	0
T6	643048	0	0	0
T17	0	68	0	0
T19	0	55	0	0
T22	0	9	0	0
T26	9248	0	0	0
T27	10026	7	0	0
T28	51105	503	0	0
T29	9695	16	0	0
T30	9296	0	0	0
T42	0	14	0	0
T52	0	25	0	0
T76	0	9661	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T27,T28

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T27,T28

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T27,T28

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T27,T28
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T27,T28

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T27,T28
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	363733187	206337	0	0
DepthKnown_A	363733187	363537524	0	0
RvalidKnown_A	363733187	363537524	0	0
WreadyKnown_A	363733187	363537524	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	363733187	206337	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	206337	0	0
T1	8835	5	0	0
T2	7694	0	0	0
T3	325909	0	0	0
T4	362558	0	0	0
T6	643048	0	0	0
T17	0	15	0	0
T19	0	55	0	0
T22	0	7	0	0
T26	9248	0	0	0
T27	10026	7	0	0
T28	51105	107	0	0
T29	9695	8	0	0
T30	9296	0	0	0
T42	0	3	0	0
T52	0	25	0	0
T76	0	5767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	206337	0	0
T1	8835	5	0	0
T2	7694	0	0	0
T3	325909	0	0	0
T4	362558	0	0	0
T6	643048	0	0	0
T17	0	15	0	0
T19	0	55	0	0
T22	0	7	0	0
T26	9248	0	0	0
T27	10026	7	0	0
T28	51105	107	0	0
T29	9695	8	0	0
T30	9296	0	0	0
T42	0	3	0	0
T52	0	25	0	0
T76	0	5767	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T27,T28

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T27,T28

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T27,T28
1	1	0	Not Covered
1	1	1	Covered	T1,T27,T28

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T27,T28

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T27,T28

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T17
1	0	Covered	T1,T27,T28
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T27,T28
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T27,T28

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T27,T28
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	363733187	359188	0	0
DepthKnown_A	363733187	363537524	0	0
RvalidKnown_A	363733187	363537524	0	0
WreadyKnown_A	363733187	363537524	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	363733187	359188	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	359188	0	0
T1	8835	27	0	0
T2	7694	0	0	0
T3	325909	0	0	0
T4	362558	0	0	0
T6	643048	0	0	0
T17	0	68	0	0
T19	0	55	0	0
T22	0	7	0	0
T26	9248	0	0	0
T27	10026	7	0	0
T28	51105	503	0	0
T29	9695	8	0	0
T30	9296	0	0	0
T42	0	3	0	0
T52	0	25	0	0
T76	0	5767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	363537524	0	0
T1	8835	8741	0	0
T2	7694	7603	0	0
T3	325909	325835	0	0
T4	362558	362504	0	0
T6	643048	642984	0	0
T26	9248	9155	0	0
T27	10026	9962	0	0
T28	51105	51033	0	0
T29	9695	9595	0	0
T30	9296	9205	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	363733187	359188	0	0
T1	8835	27	0	0
T2	7694	0	0	0
T3	325909	0	0	0
T4	362558	0	0	0
T6	643048	0	0	0
T17	0	68	0	0
T19	0	55	0	0
T22	0	7	0	0
T26	9248	0	0	0
T27	10026	7	0	0
T28	51105	503	0	0
T29	9695	8	0	0
T30	9296	0	0	0
T42	0	3	0	0
T52	0	25	0	0
T76	0	5767	0	0