Module Definition
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Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_wake_events_cdc 68.40 94.12 46.15 83.33 50.00
tb.dut.u_reg.u_wake_control_cdc 97.73 100.00 90.91 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.40 94.12 46.15 83.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 90.62 52.94 84.21 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.47 99.76 98.11 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 82.08 89.80 57.14 81.40 100.00
u_src_to_dst_req 56.41 92.31 33.33 100.00 0.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.13 96.08 96.43 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.47 99.76 98.11 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.88 87.50 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT6,T7,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT6,T7,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT6,T7,T8
11CoveredT6,T7,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT6,T7,T8

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T6,T7,T8
0 0 1 Covered T6,T7,T8
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T6,T7,T8
0 0 1 Covered T6,T7,T8
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 731320692 326976 0 0
DstReqKnown_A 8666222 8618588 0 0
SrcAckBusyChk_A 731320692 996 0 0
SrcBusyKnown_A 731320692 730821164 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 731320692 326976 0 0
T5 310267 0 0 0
T6 643048 463 0 0
T7 112239 672 0 0
T8 0 340 0 0
T9 0 632 0 0
T10 0 610 0 0
T11 0 404 0 0
T12 0 404 0 0
T13 0 347 0 0
T14 0 468 0 0
T15 0 392 0 0
T16 111790 0 0 0
T17 11563 0 0 0
T18 7438 0 0 0
T19 17060 0 0 0
T20 228578 0 0 0
T21 9252 0 0 0
T22 9524 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8666222 8618588 0 0
T1 114 100 0 0
T2 168 158 0 0
T3 11868 11856 0 0
T4 10182 10170 0 0
T6 15512 15498 0 0
T26 104 84 0 0
T27 160 142 0 0
T28 2090 2080 0 0
T29 272 262 0 0
T30 284 274 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 731320692 996 0 0
T5 310267 0 0 0
T6 643048 2 0 0
T7 112239 2 0 0
T8 0 2 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 2 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 0 2 0 0
T15 0 2 0 0
T16 111790 0 0 0
T17 11563 0 0 0
T18 7438 0 0 0
T19 17060 0 0 0
T20 228578 0 0 0
T21 9252 0 0 0
T22 9524 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 731320692 730821164 0 0
T1 17670 17482 0 0
T2 15388 15206 0 0
T3 651818 651670 0 0
T4 725116 725008 0 0
T6 1286096 1285968 0 0
T26 18496 18310 0 0
T27 20052 19924 0 0
T28 102210 102066 0 0
T29 19390 19190 0 0
T30 18592 18410 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
TOTAL171694.12
CONT_ASSIGN6500
ALWAYS715480.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11577100.00
CONT_ASSIGN15000
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 unreachable
71 1 1
72 1 1
73 1 1
74 unreachable
75 1 1
76 0 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 unreachable
124 unreachable
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 unreachable
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalCoveredPercent
Conditions13646.15
Logical13646.15
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T8
10Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT6,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
Branches 6 5 83.33
IF 71 3 2 66.67
IF 115 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Covered T6,T7,T8
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 365660346 0 0 0
DstReqKnown_A 4333111 4309294 0 0
SrcAckBusyChk_A 365660346 0 0 0
SrcBusyKnown_A 365660346 365410582 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365660346 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4333111 4309294 0 0
T1 57 50 0 0
T2 84 79 0 0
T3 5934 5928 0 0
T4 5091 5085 0 0
T6 7756 7749 0 0
T26 52 42 0 0
T27 80 71 0 0
T28 1045 1040 0 0
T29 136 131 0 0
T30 142 137 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365660346 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365660346 365410582 0 0
T1 8835 8741 0 0
T2 7694 7603 0 0
T3 325909 325835 0 0
T4 362558 362504 0 0
T6 643048 642984 0 0
T26 9248 9155 0 0
T27 10026 9962 0 0
T28 51105 51033 0 0
T29 9695 9595 0 0
T30 9296 9205 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT6,T7,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT6,T7,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT6,T7,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT6,T7,T8
11CoveredT6,T7,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T6,T7,T8
0 0 1 Covered T6,T7,T8
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T6,T7,T8
0 0 1 Covered T6,T7,T8
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 365660346 326976 0 0
DstReqKnown_A 4333111 4309294 0 0
SrcAckBusyChk_A 365660346 996 0 0
SrcBusyKnown_A 365660346 365410582 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365660346 326976 0 0
T5 310267 0 0 0
T6 643048 463 0 0
T7 112239 672 0 0
T8 0 340 0 0
T9 0 632 0 0
T10 0 610 0 0
T11 0 404 0 0
T12 0 404 0 0
T13 0 347 0 0
T14 0 468 0 0
T15 0 392 0 0
T16 111790 0 0 0
T17 11563 0 0 0
T18 7438 0 0 0
T19 17060 0 0 0
T20 228578 0 0 0
T21 9252 0 0 0
T22 9524 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4333111 4309294 0 0
T1 57 50 0 0
T2 84 79 0 0
T3 5934 5928 0 0
T4 5091 5085 0 0
T6 7756 7749 0 0
T26 52 42 0 0
T27 80 71 0 0
T28 1045 1040 0 0
T29 136 131 0 0
T30 142 137 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365660346 996 0 0
T5 310267 0 0 0
T6 643048 2 0 0
T7 112239 2 0 0
T8 0 2 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 2 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 0 2 0 0
T15 0 2 0 0
T16 111790 0 0 0
T17 11563 0 0 0
T18 7438 0 0 0
T19 17060 0 0 0
T20 228578 0 0 0
T21 9252 0 0 0
T22 9524 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365660346 365410582 0 0
T1 8835 8741 0 0
T2 7694 7603 0 0
T3 325909 325835 0 0
T4 362558 362504 0 0
T6 643048 642984 0 0
T26 9248 9155 0 0
T27 10026 9962 0 0
T28 51105 51033 0 0
T29 9695 9595 0 0
T30 9296 9205 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%