Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14275128	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	14584226	1		T1	41		T2	11		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28399762	1		T1	21		T2	7		T3	7
values[0x0]	229668	1		T1	17		T2	8		T3	6
values[0x1]	229924	1		T1	15		T2	3		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11377774	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	17481580	1		T1	47		T2	14		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	85942	1		T3	1		T4	83		T36	3
valid_sources[0x01]	86535	1		T4	66		T36	14		T6	507
valid_sources[0x02]	84275	1		T4	87		T36	25		T6	443
valid_sources[0x03]	124525	1		T1	1		T4	43		T36	20
valid_sources[0x04]	86439	1		T4	79		T36	14		T6	497
valid_sources[0x05]	86384	1		T4	73		T36	33		T6	446
valid_sources[0x06]	84831	1		T3	2		T4	93		T36	19
valid_sources[0x07]	115755	1		T2	4		T3	1		T4	55
valid_sources[0x08]	84319	1		T3	1		T4	90		T36	39
valid_sources[0x09]	87231	1		T1	1		T4	69		T36	16
valid_sources[0x0a]	85684	1		T29	12		T4	69		T36	47
valid_sources[0x0b]	83349	1		T4	101		T36	20		T6	433
valid_sources[0x0c]	85828	1		T4	66		T36	14		T6	500
valid_sources[0x0d]	83353	1		T1	1		T30	1		T4	58
valid_sources[0x0e]	85819	1		T4	65		T36	25		T6	484
valid_sources[0x0f]	119683	1		T4	76		T36	15		T6	543
valid_sources[0x10]	84098	1		T4	81		T36	20		T6	468
valid_sources[0x11]	85341	1		T4	73		T36	46		T6	499
valid_sources[0x12]	155899	1		T4	60		T36	13		T6	411
valid_sources[0x13]	84119	1		T32	2		T4	65		T36	29
valid_sources[0x14]	85797	1		T1	1		T4	44		T36	13
valid_sources[0x15]	86075	1		T4	74		T36	22		T6	485
valid_sources[0x16]	86325	1		T4	72		T36	1		T6	453
valid_sources[0x17]	120151	1		T4	67		T36	24		T6	499
valid_sources[0x18]	85598	1		T4	59		T36	24		T6	562
valid_sources[0x19]	172655	1		T4	78		T36	34		T6	468
valid_sources[0x1a]	84369	1		T33	1		T4	73		T36	19
valid_sources[0x1b]	86028	1		T4	70		T36	24		T6	426
valid_sources[0x1c]	249685	1		T4	63		T36	22		T6	438
valid_sources[0x1d]	83146	1		T4	66		T36	23		T6	499
valid_sources[0x1e]	227089	1		T1	3		T4	92		T36	21
valid_sources[0x1f]	84678	1		T31	3		T32	1		T4	67
valid_sources[0x20]	84407	1		T3	1		T4	60		T36	18
valid_sources[0x21]	86082	1		T1	1		T4	73		T36	37
valid_sources[0x22]	159456	1		T3	1		T4	56		T36	8
valid_sources[0x23]	84377	1		T4	52		T36	20		T6	423
valid_sources[0x24]	83993	1		T4	71		T36	13		T6	536
valid_sources[0x25]	85955	1		T32	2		T4	81		T36	9
valid_sources[0x26]	85437	1		T4	74		T36	20		T6	443
valid_sources[0x27]	173821	1		T3	1		T37	10		T4	81
valid_sources[0x28]	86634	1		T4	67		T36	12		T6	415
valid_sources[0x29]	152232	1		T4	60		T36	15		T6	478
valid_sources[0x2a]	85436	1		T26	1		T4	78		T36	33
valid_sources[0x2b]	114560	1		T4	83		T36	34		T6	398
valid_sources[0x2c]	122964	1		T4	73		T36	20		T6	484
valid_sources[0x2d]	252808	1		T4	69		T36	11		T6	455
valid_sources[0x2e]	85581	1		T1	4		T33	1		T4	67
valid_sources[0x2f]	84809	1		T4	59		T36	42		T6	442
valid_sources[0x30]	85343	1		T4	84		T36	28		T6	448
valid_sources[0x31]	162881	1		T4	85		T36	16		T6	471
valid_sources[0x32]	84997	1		T1	1		T3	1		T4	64
valid_sources[0x33]	85677	1		T4	72		T36	19		T6	509
valid_sources[0x34]	85660	1		T32	2		T4	78		T36	25
valid_sources[0x35]	85301	1		T4	72		T36	15		T6	525
valid_sources[0x36]	243894	1		T32	1		T4	87		T36	16
valid_sources[0x37]	198816	1		T3	2		T4	79		T36	12
valid_sources[0x38]	138925	1		T1	1		T4	83		T36	17
valid_sources[0x39]	85372	1		T4	97		T36	25		T6	454
valid_sources[0x3a]	106958	1		T4	59		T36	20		T6	520
valid_sources[0x3b]	84932	1		T32	1		T4	69		T36	8
valid_sources[0x3c]	86762	1		T4	65		T36	33		T6	468
valid_sources[0x3d]	85712	1		T4	71		T36	28		T6	577
valid_sources[0x3e]	85166	1		T4	79		T36	35		T6	429
valid_sources[0x3f]	84535	1		T1	1		T4	64		T36	19
valid_sources[0x40]	166336	1		T4	62		T36	46		T6	524
valid_sources[0x41]	220397	1		T4	74		T36	17		T6	496
valid_sources[0x42]	84214	1		T1	1		T4	71		T36	26
valid_sources[0x43]	187098	1		T3	1		T4	48		T36	18
valid_sources[0x44]	136386	1		T4	63		T36	26		T6	428
valid_sources[0x45]	86222	1		T30	1		T4	80		T36	17
valid_sources[0x46]	83967	1		T4	74		T36	22		T6	492
valid_sources[0x47]	103775	1		T4	94		T36	26		T6	483
valid_sources[0x48]	88085	1		T4	56		T36	16		T6	525
valid_sources[0x49]	85973	1		T1	1		T3	2		T4	59
valid_sources[0x4a]	108399	1		T4	86		T36	24		T6	468
valid_sources[0x4b]	85770	1		T1	1		T4	62		T36	8
valid_sources[0x4c]	141895	1		T4	65		T36	22		T6	388
valid_sources[0x4d]	113001	1		T4	81		T36	19		T6	440
valid_sources[0x4e]	87986	1		T4	90		T36	16		T6	513
valid_sources[0x4f]	85471	1		T4	97		T36	22		T6	406
valid_sources[0x50]	280647	1		T1	1		T4	58		T36	32
valid_sources[0x51]	85137	1		T4	73		T36	43		T6	452
valid_sources[0x52]	159706	1		T2	2		T4	73		T36	21
valid_sources[0x53]	86507	1		T4	59		T36	16		T6	452
valid_sources[0x54]	88018	1		T4	61		T36	27		T6	528
valid_sources[0x55]	85892	1		T4	78		T36	3		T6	501
valid_sources[0x56]	84842	1		T3	1		T4	49		T36	37
valid_sources[0x57]	85530	1		T4	83		T36	51		T6	498
valid_sources[0x58]	84208	1		T4	68		T36	43		T6	432
valid_sources[0x59]	87223	1		T4	74		T34	1		T36	5
valid_sources[0x5a]	109928	1		T1	1		T4	76		T36	28
valid_sources[0x5b]	280038	1		T4	56		T36	20		T6	593
valid_sources[0x5c]	125946	1		T3	1		T4	68		T36	32
valid_sources[0x5d]	86380	1		T38	1		T4	76		T36	23
valid_sources[0x5e]	86547	1		T1	1		T4	63		T36	29
valid_sources[0x5f]	85944	1		T4	69		T36	28		T6	452
valid_sources[0x60]	107384	1		T2	2		T4	71		T36	13
valid_sources[0x61]	84738	1		T4	71		T36	8		T6	490
valid_sources[0x62]	85513	1		T1	3		T4	85		T36	18
valid_sources[0x63]	86206	1		T1	1		T4	69		T36	32
valid_sources[0x64]	84663	1		T1	1		T4	50		T36	11
valid_sources[0x65]	85109	1		T2	1		T4	59		T36	4
valid_sources[0x66]	84563	1		T4	94		T36	30		T6	491
valid_sources[0x67]	85886	1		T4	65		T36	9		T6	471
valid_sources[0x68]	85326	1		T4	66		T36	32		T6	448
valid_sources[0x69]	86474	1		T1	1		T4	61		T36	39
valid_sources[0x6a]	84960	1		T4	79		T36	22		T6	467
valid_sources[0x6b]	85876	1		T2	2		T4	94		T36	21
valid_sources[0x6c]	125414	1		T4	63		T36	28		T6	473
valid_sources[0x6d]	228119	1		T1	2		T4	56		T36	6
valid_sources[0x6e]	86572	1		T4	67		T36	25		T6	503
valid_sources[0x6f]	84606	1		T1	1		T4	90		T36	19
valid_sources[0x70]	85517	1		T32	1		T4	48		T36	5
valid_sources[0x71]	123801	1		T4	90		T36	32		T6	506
valid_sources[0x72]	323908	1		T4	74		T36	9		T6	476
valid_sources[0x73]	190293	1		T4	66		T36	14		T6	522
valid_sources[0x74]	125600	1		T4	58		T36	26		T6	403
valid_sources[0x75]	86594	1		T30	1		T32	1		T4	78
valid_sources[0x76]	324046	1		T1	2		T4	78		T36	35
valid_sources[0x77]	85467	1		T4	70		T36	25		T6	475
valid_sources[0x78]	140938	1		T26	8		T4	65		T36	25
valid_sources[0x79]	85367	1		T1	3		T31	1		T4	85
valid_sources[0x7a]	85095	1		T4	72		T36	33		T6	514
valid_sources[0x7b]	86934	1		T2	1		T4	63		T36	31
valid_sources[0x7c]	85489	1		T4	52		T36	36		T6	474
valid_sources[0x7d]	84766	1		T4	61		T36	17		T6	473
valid_sources[0x7e]	85378	1		T1	1		T4	60		T36	8
valid_sources[0x7f]	85760	1		T38	1		T4	74		T36	1
valid_sources[0x80]	193917	1		T2	2		T32	1		T4	68

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14226290

1

T1

15

T2

4

T3

3

values[0x0]

all_enables

biggest_size

185489

1

T1

15

T2

7

T3

6

values[0x1]

all_enables

biggest_size

172447

1

T1

11

T3

3

T30

2