Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14288239	1		T1	12		T2	7		T3	9
full_word	14585133	1		T1	41		T2	11		T3	12

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	28873092	1		T1	53		T2	18		T3	21
auto[TlIntgErrCmd]	96	1		T210	8		T212	3		T237	4
auto[TlIntgErrData]	107	1		T210	9		T212	8		T237	2
auto[TlIntgErrBoth]	77	1		T210	3		T212	9		T237	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28401450	1		T1	21		T2	7		T3	7
auto[1]	471922	1		T1	32		T2	11		T3	14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14174867	1		T1	6		T2	3		T3	4
auto[TlIntgErrNone]	partial	auto[1]	113119	1		T1	6		T2	4		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	14226443	1		T1	15		T2	4		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	358663	1		T1	26		T2	7		T3	9
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T210	4		T212	1		T237	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1		T210	3		T212	2		T237	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T252	2		T302	1		T303	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T210	1		T304	3		-	-
auto[TlIntgErrData]	partial	auto[0]	53	1		T210	4		T212	2		T237	1
auto[TlIntgErrData]	partial	auto[1]	42	1		T210	5		T212	4		T237	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T212	2		T253	1		T302	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T305	1		T306	2		T307	2
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T210	1		T212	5		T237	2
auto[TlIntgErrBoth]	partial	auto[1]	41	1		T210	2		T212	4		T237	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T250	1		T308	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T250	2		T309	1		T304	1