Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	357882415	9898	0	0
ep_in_enable_rd_A	357882415	2163	0	0
ep_out_enable_rd_A	357882415	2264	0	0
in_iso_rd_A	357882415	2317	0	0
intr_enable_rd_A	357882415	2888	0	0
out_iso_rd_A	357882415	2265	0	0
phy_config_rd_A	357882415	1605	0	0
phy_pins_drive_rd_A	357882415	1902	0	0
rxenable_setup_rd_A	357882415	2225	0	0
set_nak_out_rd_A	357882415	2229	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	9898	0	0
T210	44435	8	0	0
T211	7342	616	0	0
T212	41893	7	0	0
T232	3315	280	0	0
T233	5874	1083	0	0
T237	45453	3	0	0
T239	9730	721	0	0
T242	7145	19	0	0
T249	7174	392	0	0
T250	44996	5	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	2163	0	0
T216	9004	34	0	0
T237	45453	139	0	0
T263	82180	440	0	0
T266	5085	72	0	0
T267	3913	6	0	0
T268	28447	148	0	0
T269	4350	8	0	0
T270	4557	44	0	0
T280	13891	37	0	0
T282	9612	40	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	2264	0	0
T216	9004	73	0	0
T237	45453	135	0	0
T263	82180	429	0	0
T266	5085	11	0	0
T267	3913	16	0	0
T268	28447	130	0	0
T269	4350	48	0	0
T270	4557	34	0	0
T280	13891	33	0	0
T282	9612	43	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	2317	0	0
T216	9004	32	0	0
T237	45453	122	0	0
T263	82180	467	0	0
T266	5085	68	0	0
T267	3913	7	0	0
T268	28447	117	0	0
T269	4350	5	0	0
T270	4557	43	0	0
T280	13891	8	0	0
T282	9612	54	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	2888	0	0
T216	9004	64	0	0
T237	45453	162	0	0
T263	82180	421	0	0
T266	5085	75	0	0
T267	3913	82	0	0
T268	28447	129	0	0
T280	13891	39	0	0
T283	2653	13	0	0
T284	2428	21	0	0
T285	2287	12	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	2265	0	0
T216	9004	28	0	0
T237	45453	206	0	0
T263	82180	427	0	0
T266	5085	76	0	0
T267	3913	95	0	0
T268	28447	133	0	0
T269	4350	36	0	0
T270	4557	31	0	0
T280	13891	38	0	0
T282	9612	10	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	1605	0	0
T216	9004	41	0	0
T237	45453	119	0	0
T263	82180	430	0	0
T266	5085	34	0	0
T267	3913	29	0	0
T268	28447	122	0	0
T269	4350	20	0	0
T272	4256	36	0	0
T280	13891	21	0	0
T282	9612	7	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	1902	0	0
T216	9004	78	0	0
T237	45453	104	0	0
T244	17502	4	0	0
T263	82180	448	0	0
T266	5085	34	0	0
T267	3913	28	0	0
T268	28447	95	0	0
T270	4557	16	0	0
T280	13891	31	0	0
T282	9612	28	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	2225	0	0
T216	9004	39	0	0
T237	45453	74	0	0
T263	82180	451	0	0
T266	5085	92	0	0
T267	3913	76	0	0
T268	28447	144	0	0
T269	4350	4	0	0
T270	4557	5	0	0
T280	13891	29	0	0
T282	9612	68	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357882415	2229	0	0
T216	9004	38	0	0
T237	45453	134	0	0
T263	82180	438	0	0
T267	3913	78	0	0
T268	28447	134	0	0
T269	4350	58	0	0
T270	4557	30	0	0
T272	4256	9	0	0
T280	13891	20	0	0
T282	9612	48	0	0