dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.06 100.00 88.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.usbdev_avoutfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.06 100.00 88.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.usbdev_rxfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.53 100.00 86.11 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.33 95.00 75.00 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.43 98.59 78.81 92.31 100.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.62 100.00 62.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.64 95.00 72.22 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.43 98.59 78.81 92.31 100.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.32 95.00 77.27 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.43 98.59 78.81 92.31 100.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73

Go back
Module Instances:
tb.dut.usbdev_avsetupfifo
tb.dut.usbdev_avoutfifo
tb.dut.usbdev_rxfifo
tb.dut.u_reg.u_socket.fifo_h.reqfifo
tb.dut.u_reg.u_socket.fifo_h.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Line Coverage for Instance : tb.dut.usbdev_avsetupfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T32,T33

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT74,T75,T92
110Not Covered
111CoveredT1,T32,T33

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T32,T33
110Not Covered
111CoveredT1,T32,T33

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 356226268 136077050 0 0
DepthKnown_A 356226268 356030593 0 0
RvalidKnown_A 356226268 356030593 0 0
WreadyKnown_A 356226268 356030593 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 356226268 136077050 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 136077050 0 0
T1 11649 555 0 0
T2 8535 0 0 0
T3 156225 0 0 0
T4 0 193113 0 0
T5 0 218298 0 0
T6 0 246607 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 574 0 0
T33 7397 584 0 0
T35 0 578 0 0
T36 0 969547 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T88 0 137449 0 0
T91 0 202552 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 136077050 0 0
T1 11649 555 0 0
T2 8535 0 0 0
T3 156225 0 0 0
T4 0 193113 0 0
T5 0 218298 0 0
T6 0 246607 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 574 0 0
T33 7397 584 0 0
T35 0 578 0 0
T36 0 969547 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T88 0 137449 0 0
T91 0 202552 0 0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.usbdev_avoutfifo
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT73,T93
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.usbdev_avoutfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 356226268 161606358 0 0
DepthKnown_A 356226268 356030593 0 0
RvalidKnown_A 356226268 356030593 0 0
WreadyKnown_A 356226268 356030593 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 356226268 161606358 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 161606358 0 0
T1 11649 1866 0 0
T2 8535 340 0 0
T3 156225 308 0 0
T4 0 193023 0 0
T5 0 218282 0 0
T29 7887 304 0 0
T30 8493 2724 0 0
T31 7867 1933 0 0
T32 10086 400 0 0
T33 7397 0 0 0
T35 0 1913 0 0
T37 7294 0 0 0
T38 2043 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 161606358 0 0
T1 11649 1866 0 0
T2 8535 340 0 0
T3 156225 308 0 0
T4 0 193023 0 0
T5 0 218282 0 0
T29 7887 304 0 0
T30 8493 2724 0 0
T31 7867 1933 0 0
T32 10086 400 0 0
T33 7397 0 0 0
T35 0 1913 0 0
T37 7294 0 0 0
T38 2043 0 0 0

Line Coverage for Instance : tb.dut.usbdev_rxfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.usbdev_rxfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT62,T63,T64
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.usbdev_rxfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.usbdev_rxfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 356226268 19229316 0 0
DepthKnown_A 356226268 356030593 0 0
RvalidKnown_A 356226268 356030593 0 0
WreadyKnown_A 356226268 356030593 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 356226268 19229316 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 19229316 0 0
T1 11649 197 0 0
T2 8535 97 0 0
T3 156225 112 0 0
T4 0 3029 0 0
T5 0 718 0 0
T29 7887 1309 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 217 0 0
T33 7397 1007 0 0
T35 0 209 0 0
T36 0 564212 0 0
T37 7294 0 0 0
T38 2043 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 19229316 0 0
T1 11649 197 0 0
T2 8535 97 0 0
T3 156225 112 0 0
T4 0 3029 0 0
T5 0 718 0 0
T29 7887 1309 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 217 0 0
T33 7397 1007 0 0
T35 0 209 0 0
T36 0 564212 0 0
T37 7294 0 0 0
T38 2043 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 357882415 29110037 0 0
DepthKnown_A 357882415 357629745 0 0
RvalidKnown_A 357882415 357629745 0 0
WreadyKnown_A 357882415 357629745 0 0
gen_passthru_fifo.paramCheckPass 2735 2735 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 29110037 0 0
T1 11649 53 0 0
T2 8535 18 0 0
T3 156225 21 0 0
T29 7887 12 0 0
T30 8493 10 0 0
T31 7867 10 0 0
T32 10086 31 0 0
T33 7397 13 0 0
T37 7294 11 0 0
T38 2043 7 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 357882415 38865909 0 0
DepthKnown_A 357882415 357629745 0 0
RvalidKnown_A 357882415 357629745 0 0
WreadyKnown_A 357882415 357629745 0 0
gen_passthru_fifo.paramCheckPass 2735 2735 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 38865909 0 0
T1 11649 53 0 0
T2 8535 58 0 0
T3 156225 77 0 0
T29 7887 12 0 0
T30 8493 35 0 0
T31 7867 10 0 0
T32 10086 144 0 0
T33 7397 13 0 0
T37 7294 11 0 0
T38 2043 7 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 357882415 396678 0 0
DepthKnown_A 357882415 357629745 0 0
RvalidKnown_A 357882415 357629745 0 0
WreadyKnown_A 357882415 357629745 0 0
gen_passthru_fifo.paramCheckPass 2735 2735 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 396678 0 0
T1 11649 30 0 0
T2 8535 1 0 0
T3 156225 0 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 8 0 0
T33 7397 0 0 0
T35 0 21 0 0
T36 0 1150 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T50 0 7 0 0
T51 0 90 0 0
T52 0 3893 0 0
T89 0 16 0 0
T90 0 15 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 357882415 813357 0 0
DepthKnown_A 357882415 357629745 0 0
RvalidKnown_A 357882415 357629745 0 0
WreadyKnown_A 357882415 357629745 0 0
gen_passthru_fifo.paramCheckPass 2735 2735 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 813357 0 0
T1 11649 30 0 0
T2 8535 6 0 0
T3 156225 0 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 34 0 0
T33 7397 0 0 0
T35 0 21 0 0
T36 0 1150 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T50 0 24 0 0
T51 0 90 0 0
T52 0 3893 0 0
T89 0 16 0 0
T90 0 15 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 357882415 28650708 0 0
DepthKnown_A 357882415 357629745 0 0
RvalidKnown_A 357882415 357629745 0 0
WreadyKnown_A 357882415 357629745 0 0
gen_passthru_fifo.paramCheckPass 2735 2735 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 28650708 0 0
T1 11649 23 0 0
T2 8535 17 0 0
T3 156225 21 0 0
T29 7887 12 0 0
T30 8493 10 0 0
T31 7867 10 0 0
T32 10086 23 0 0
T33 7397 13 0 0
T37 7294 11 0 0
T38 2043 7 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 357882415 38052552 0 0
DepthKnown_A 357882415 357629745 0 0
RvalidKnown_A 357882415 357629745 0 0
WreadyKnown_A 357882415 357629745 0 0
gen_passthru_fifo.paramCheckPass 2735 2735 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 38052552 0 0
T1 11649 23 0 0
T2 8535 52 0 0
T3 156225 77 0 0
T29 7887 12 0 0
T30 8493 35 0 0
T31 7867 10 0 0
T32 10086 110 0 0
T33 7397 13 0 0
T37 7294 11 0 0
T38 2043 7 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357882415 357629745 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T32
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T32

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T32

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T32,T35
110Not Covered
111CoveredT1,T2,T32

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T32
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T32


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 356226268 738779 0 0
DepthKnown_A 356226268 356030593 0 0
RvalidKnown_A 356226268 356030593 0 0
WreadyKnown_A 356226268 356030593 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 356226268 738779 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 738779 0 0
T1 11649 30 0 0
T2 8535 6 0 0
T3 156225 0 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 34 0 0
T33 7397 0 0 0
T35 0 21 0 0
T36 0 1150 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T50 0 24 0 0
T51 0 90 0 0
T52 0 3893 0 0
T89 0 16 0 0
T90 0 15 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 738779 0 0
T1 11649 30 0 0
T2 8535 6 0 0
T3 156225 0 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 34 0 0
T33 7397 0 0 0
T35 0 21 0 0
T36 0 1150 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T50 0 24 0 0
T51 0 90 0 0
T52 0 3893 0 0
T89 0 16 0 0
T90 0 15 0 0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
TotalCoveredPercent
Conditions161062.50
Logical161062.50
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T32
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T32

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T32

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT1,T2,T32

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T32
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T32


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 356226268 209432 0 0
DepthKnown_A 356226268 356030593 0 0
RvalidKnown_A 356226268 356030593 0 0
WreadyKnown_A 356226268 356030593 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 356226268 209432 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 209432 0 0
T1 11649 14 0 0
T2 8535 1 0 0
T3 156225 0 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 3 0 0
T33 7397 0 0 0
T35 0 15 0 0
T36 0 424 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T50 0 7 0 0
T51 0 90 0 0
T52 0 2389 0 0
T89 0 16 0 0
T90 0 9 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 209432 0 0
T1 11649 14 0 0
T2 8535 1 0 0
T3 156225 0 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 3 0 0
T33 7397 0 0 0
T35 0 15 0 0
T36 0 424 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T50 0 7 0 0
T51 0 90 0 0
T52 0 2389 0 0
T89 0 16 0 0
T90 0 9 0 0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T32,T50
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T32

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T32

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T32,T35
110Not Covered
111CoveredT1,T2,T32

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T32

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T32

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T32,T50
10CoveredT1,T2,T32
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T32
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T32


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 356226268 431498 0 0
DepthKnown_A 356226268 356030593 0 0
RvalidKnown_A 356226268 356030593 0 0
WreadyKnown_A 356226268 356030593 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 356226268 431498 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 431498 0 0
T1 11649 14 0 0
T2 8535 6 0 0
T3 156225 0 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 13 0 0
T33 7397 0 0 0
T35 0 15 0 0
T36 0 424 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T50 0 24 0 0
T51 0 90 0 0
T52 0 2389 0 0
T89 0 16 0 0
T90 0 9 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 356030593 0 0
T1 11649 11553 0 0
T2 8535 8480 0 0
T3 156225 156169 0 0
T29 7887 7803 0 0
T30 8493 8443 0 0
T31 7867 7799 0 0
T32 10086 9999 0 0
T33 7397 7303 0 0
T37 7294 7229 0 0
T38 2043 1954 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 356226268 431498 0 0
T1 11649 14 0 0
T2 8535 6 0 0
T3 156225 0 0 0
T29 7887 0 0 0
T30 8493 0 0 0
T31 7867 0 0 0
T32 10086 13 0 0
T33 7397 0 0 0
T35 0 15 0 0
T36 0 424 0 0
T37 7294 0 0 0
T38 2043 0 0 0
T50 0 24 0 0
T51 0 90 0 0
T52 0 2389 0 0
T89 0 16 0 0
T90 0 9 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%