Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14799691	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15116321	1		T1	6		T2	5		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29434017	1		T1	4		T2	4		T3	3
values[0x0]	239893	1		T1	6		T2	3		T3	4
values[0x1]	242102	1		T1	4		T2	2		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11794520	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18121492	1		T1	8		T2	8		T3	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	105108	1		T2	2		T28	1		T29	13
valid_sources[0x01]	83376	1		T29	18		T4	358		T5	225
valid_sources[0x02]	82536	1		T29	8		T4	291		T5	187
valid_sources[0x03]	258852	1		T29	15		T4	429		T5	235
valid_sources[0x04]	83285	1		T29	17		T4	387		T17	4
valid_sources[0x05]	84986	1		T27	1		T29	31		T4	417
valid_sources[0x06]	84026	1		T29	18		T4	436		T31	11
valid_sources[0x07]	84370	1		T29	9		T4	332		T31	4
valid_sources[0x08]	83434	1		T3	1		T29	21		T4	319
valid_sources[0x09]	243657	1		T29	23		T4	339		T33	3
valid_sources[0x0a]	83483	1		T29	16		T4	369		T5	213
valid_sources[0x0b]	83778	1		T29	18		T4	427		T5	197
valid_sources[0x0c]	85044	1		T29	15		T4	306		T5	216
valid_sources[0x0d]	84598	1		T29	19		T4	346		T7	1
valid_sources[0x0e]	85715	1		T29	17		T4	372		T5	193
valid_sources[0x0f]	117001	1		T29	14		T4	274		T5	211
valid_sources[0x10]	169760	1		T29	17		T4	384		T7	1
valid_sources[0x11]	84528	1		T29	16		T4	457		T7	2
valid_sources[0x12]	84400	1		T29	10		T4	403		T5	220
valid_sources[0x13]	84732	1		T29	11		T4	385		T32	7
valid_sources[0x14]	83549	1		T29	26		T4	398		T7	1
valid_sources[0x15]	184521	1		T29	27		T4	274		T5	199
valid_sources[0x16]	86714	1		T1	3		T29	12		T4	368
valid_sources[0x17]	83794	1		T29	11		T4	296		T17	13
valid_sources[0x18]	178844	1		T29	15		T4	345		T5	233
valid_sources[0x19]	83583	1		T29	23		T4	400		T5	251
valid_sources[0x1a]	237822	1		T29	8		T4	378		T31	12
valid_sources[0x1b]	135595	1		T29	19		T4	408		T7	1
valid_sources[0x1c]	83968	1		T26	28		T34	1		T29	17
valid_sources[0x1d]	83468	1		T28	1		T29	16		T4	316
valid_sources[0x1e]	83237	1		T29	17		T4	410		T5	191
valid_sources[0x1f]	84325	1		T29	19		T4	426		T5	197
valid_sources[0x20]	215014	1		T29	22		T4	377		T5	207
valid_sources[0x21]	83737	1		T29	17		T4	428		T7	1
valid_sources[0x22]	375589	1		T29	21		T4	397		T5	198
valid_sources[0x23]	187367	1		T27	1		T29	21		T4	344
valid_sources[0x24]	84063	1		T29	21		T4	280		T5	210
valid_sources[0x25]	297365	1		T29	10		T4	338		T5	228
valid_sources[0x26]	81981	1		T29	33		T4	352		T5	233
valid_sources[0x27]	361407	1		T29	17		T4	344		T5	214
valid_sources[0x28]	83421	1		T29	14		T4	400		T5	232
valid_sources[0x29]	84278	1		T29	9		T4	385		T17	5
valid_sources[0x2a]	83693	1		T28	1		T29	17		T4	327
valid_sources[0x2b]	82730	1		T29	15		T4	446		T7	1
valid_sources[0x2c]	83860	1		T29	16		T4	398		T5	233
valid_sources[0x2d]	84405	1		T29	13		T4	387		T17	2
valid_sources[0x2e]	84270	1		T29	14		T4	330		T5	206
valid_sources[0x2f]	85495	1		T27	1		T28	1		T29	13
valid_sources[0x30]	83063	1		T29	9		T4	264		T7	1
valid_sources[0x31]	84048	1		T29	21		T4	333		T17	7
valid_sources[0x32]	85252	1		T29	26		T4	331		T7	1
valid_sources[0x33]	84347	1		T29	19		T4	303		T5	197
valid_sources[0x34]	144791	1		T29	11		T4	355		T7	1
valid_sources[0x35]	85691	1		T29	11		T4	277		T5	221
valid_sources[0x36]	83948	1		T29	14		T4	342		T5	204
valid_sources[0x37]	82942	1		T34	1		T29	12		T4	354
valid_sources[0x38]	84789	1		T2	2		T29	9		T4	343
valid_sources[0x39]	82920	1		T29	7		T4	370		T5	189
valid_sources[0x3a]	83285	1		T29	23		T4	403		T5	207
valid_sources[0x3b]	84830	1		T28	1		T29	16		T4	338
valid_sources[0x3c]	85398	1		T29	7		T4	350		T7	1
valid_sources[0x3d]	82961	1		T29	21		T4	460		T5	184
valid_sources[0x3e]	85219	1		T28	1		T29	20		T4	438
valid_sources[0x3f]	114051	1		T29	11		T4	416		T5	231
valid_sources[0x40]	83571	1		T29	18		T4	442		T31	11
valid_sources[0x41]	83760	1		T1	7		T29	16		T4	340
valid_sources[0x42]	192505	1		T29	18		T4	377		T5	210
valid_sources[0x43]	83689	1		T28	1		T29	16		T4	421
valid_sources[0x44]	131813	1		T28	1		T29	18		T4	376
valid_sources[0x45]	82972	1		T29	17		T4	419		T17	3
valid_sources[0x46]	84063	1		T28	1		T29	14		T4	358
valid_sources[0x47]	334677	1		T29	15		T4	432		T17	3
valid_sources[0x48]	217034	1		T29	3		T4	332		T17	6
valid_sources[0x49]	83698	1		T3	4		T29	23		T4	458
valid_sources[0x4a]	82697	1		T29	5		T4	408		T17	5
valid_sources[0x4b]	85052	1		T29	9		T4	457		T7	1
valid_sources[0x4c]	127196	1		T3	1		T29	23		T4	373
valid_sources[0x4d]	84240	1		T29	17		T4	412		T7	2
valid_sources[0x4e]	83240	1		T29	6		T4	338		T5	232
valid_sources[0x4f]	122923	1		T29	25		T4	382		T7	1
valid_sources[0x50]	83797	1		T27	1		T29	22		T4	425
valid_sources[0x51]	174736	1		T29	10		T4	352		T5	203
valid_sources[0x52]	83425	1		T29	7		T4	423		T5	197
valid_sources[0x53]	169572	1		T28	1		T29	12		T4	401
valid_sources[0x54]	84455	1		T29	11		T4	363		T5	216
valid_sources[0x55]	83737	1		T29	10		T4	363		T5	185
valid_sources[0x56]	82777	1		T29	23		T4	485		T17	7
valid_sources[0x57]	131312	1		T29	13		T4	364		T17	12
valid_sources[0x58]	82686	1		T29	18		T4	478		T5	241
valid_sources[0x59]	84528	1		T27	2		T29	10		T4	378
valid_sources[0x5a]	221770	1		T29	9		T4	435		T7	1
valid_sources[0x5b]	84567	1		T29	10		T4	348		T5	223
valid_sources[0x5c]	84076	1		T29	11		T4	438		T31	9
valid_sources[0x5d]	150153	1		T29	19		T4	336		T5	218
valid_sources[0x5e]	83408	1		T29	15		T4	377		T7	2
valid_sources[0x5f]	224733	1		T29	11		T4	370		T7	1
valid_sources[0x60]	84729	1		T29	6		T4	256		T7	1
valid_sources[0x61]	135633	1		T29	18		T4	327		T5	238
valid_sources[0x62]	83144	1		T29	11		T4	365		T5	227
valid_sources[0x63]	82393	1		T29	15		T4	322		T31	7
valid_sources[0x64]	84032	1		T29	10		T4	440		T7	3
valid_sources[0x65]	89921	1		T29	12		T4	322		T7	2
valid_sources[0x66]	84304	1		T29	21		T4	378		T5	208
valid_sources[0x67]	110336	1		T27	1		T29	12		T4	403
valid_sources[0x68]	85592	1		T1	1		T29	19		T4	371
valid_sources[0x69]	197637	1		T29	6		T4	272		T5	234
valid_sources[0x6a]	82909	1		T29	22		T4	431		T7	1
valid_sources[0x6b]	84621	1		T29	11		T4	423		T7	1
valid_sources[0x6c]	84255	1		T1	3		T2	1		T29	19
valid_sources[0x6d]	87623	1		T29	13		T4	384		T7	3
valid_sources[0x6e]	158156	1		T29	21		T4	406		T31	2
valid_sources[0x6f]	116078	1		T29	19		T4	386		T5	205
valid_sources[0x70]	110109	1		T29	10		T4	308		T5	217
valid_sources[0x71]	149715	1		T29	8		T4	405		T7	1
valid_sources[0x72]	84387	1		T29	9		T4	342		T5	197
valid_sources[0x73]	84080	1		T29	10		T4	341		T5	205
valid_sources[0x74]	88582	1		T29	20		T4	311		T5	208
valid_sources[0x75]	83882	1		T29	15		T4	349		T5	185
valid_sources[0x76]	82717	1		T29	12		T4	279		T7	1
valid_sources[0x77]	156893	1		T29	9		T35	10		T4	459
valid_sources[0x78]	86061	1		T29	15		T4	323		T5	205
valid_sources[0x79]	83109	1		T28	1		T29	18		T4	324
valid_sources[0x7a]	83522	1		T29	26		T4	319		T7	1
valid_sources[0x7b]	166707	1		T29	14		T4	393		T5	193
valid_sources[0x7c]	82834	1		T29	24		T4	329		T17	2
valid_sources[0x7d]	249635	1		T29	20		T4	259		T33	1
valid_sources[0x7e]	163104	1		T29	23		T4	395		T5	189
valid_sources[0x7f]	85641	1		T28	1		T29	13		T30	13
valid_sources[0x80]	83759	1		T29	15		T4	335		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14739395

1

T1

2

T3

1

T26

19

values[0x0]

all_enables

biggest_size

194556

1

T1

4

T2

3

T3

3

values[0x1]

all_enables

biggest_size

182370

1

T2

2

T3

2

T26

2