Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14814371	1		T1	8		T2	4		T3	6
full_word	15117298	1		T1	6		T2	5		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29931339	1		T1	14		T2	9		T3	12
auto[TlIntgErrCmd]	107	1		T240	9		T247	4		T265	5
auto[TlIntgErrData]	105	1		T240	6		T246	5		T247	7
auto[TlIntgErrBoth]	118	1		T240	5		T246	5		T247	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29435974	1		T1	4		T2	4		T3	3
auto[1]	495695	1		T1	10		T2	5		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14696270	1		T1	2		T2	4		T3	2
auto[TlIntgErrNone]	partial	auto[1]	117791	1		T1	6		T3	4		T26	4
auto[TlIntgErrNone]	full_word	auto[0]	14739572	1		T1	2		T3	1		T26	19
auto[TlIntgErrNone]	full_word	auto[1]	377706	1		T1	4		T2	5		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T240	5		T247	1		T265	1
auto[TlIntgErrCmd]	partial	auto[1]	68	1		T240	4		T247	2		T265	4
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T247	1		T298	1		T305	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T240	3		T246	1		T247	2
auto[TlIntgErrData]	partial	auto[1]	53	1		T240	3		T246	4		T247	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T247	1		T265	1		T298	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T247	1		T306	1		T307	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1		T240	1		T246	3		T247	4
auto[TlIntgErrBoth]	partial	auto[1]	63	1		T240	4		T246	1		T247	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T265	1		T298	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T246	1		T265	1		T298	1