Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	370840963	11166	0	0
ep_in_enable_rd_A	370840963	3486	0	0
ep_out_enable_rd_A	370840963	3406	0	0
in_iso_rd_A	370840963	3621	0	0
intr_enable_rd_A	370840963	4522	0	0
out_iso_rd_A	370840963	3148	0	0
phy_config_rd_A	370840963	2097	0	0
phy_pins_drive_rd_A	370840963	2646	0	0
rxenable_setup_rd_A	370840963	3982	0	0
set_nak_out_rd_A	370840963	3339	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	11166	0	0
T217	8701	393	0	0
T218	8683	487	0	0
T219	5416	10	0	0
T240	46840	4	0	0
T241	4913	18	0	0
T245	7606	430	0	0
T246	19213	3	0	0
T247	32693	4	0	0
T256	7335	17	0	0
T264	6347	37	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	3486	0	0
T220	14587	71	0	0
T221	32377	227	0	0
T240	46840	348	0	0
T288	3764	59	0	0
T295	18781	70	0	0
T296	7659	26	0	0
T297	9961	51	0	0
T298	42959	556	0	0
T299	24091	159	0	0
T300	18910	46	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	3406	0	0
T220	14587	21	0	0
T221	32377	262	0	0
T240	46840	380	0	0
T288	3764	62	0	0
T295	18781	86	0	0
T296	7659	7	0	0
T297	9961	17	0	0
T298	42959	529	0	0
T299	24091	243	0	0
T301	2745	23	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	3621	0	0
T220	14587	37	0	0
T221	32377	251	0	0
T240	46840	318	0	0
T288	3764	44	0	0
T295	18781	144	0	0
T296	7659	23	0	0
T297	9961	51	0	0
T298	42959	608	0	0
T299	24091	221	0	0
T300	18910	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	4522	0	0
T220	14587	50	0	0
T221	32377	226	0	0
T226	2025	18	0	0
T229	2249	18	0	0
T240	46840	386	0	0
T286	3171	25	0	0
T288	3764	66	0	0
T302	3334	11	0	0
T303	3023	8	0	0
T304	1772	7	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	3148	0	0
T220	14587	53	0	0
T221	32377	200	0	0
T240	46840	263	0	0
T286	3171	45	0	0
T288	3764	42	0	0
T295	18781	151	0	0
T296	7659	16	0	0
T297	9961	55	0	0
T298	42959	314	0	0
T301	2745	6	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	2097	0	0
T220	14587	93	0	0
T221	32377	208	0	0
T240	46840	175	0	0
T286	3171	4	0	0
T288	3764	52	0	0
T295	18781	59	0	0
T296	7659	16	0	0
T297	9961	20	0	0
T298	42959	217	0	0
T299	24091	167	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	2646	0	0
T220	14587	47	0	0
T221	32377	226	0	0
T240	46840	154	0	0
T286	3171	9	0	0
T288	3764	68	0	0
T295	18781	85	0	0
T296	7659	45	0	0
T297	9961	53	0	0
T298	42959	502	0	0
T299	24091	161	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	3982	0	0
T220	14587	41	0	0
T221	32377	226	0	0
T240	46840	339	0	0
T286	3171	2	0	0
T288	3764	106	0	0
T295	18781	205	0	0
T296	7659	22	0	0
T297	9961	42	0	0
T298	42959	663	0	0
T299	24091	282	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370840963	3339	0	0
T220	14587	46	0	0
T221	32377	195	0	0
T240	46840	318	0	0
T286	3171	43	0	0
T288	3764	56	0	0
T295	18781	117	0	0
T296	7659	29	0	0
T297	9961	57	0	0
T298	42959	439	0	0
T301	2745	17	0	0