Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	371	1		T1	8		T3	8		T7	2
all_values[1]	371	1		T1	8		T3	8		T7	2
all_values[2]	371	1		T1	8		T3	8		T7	2
all_values[3]	371	1		T1	8		T3	8		T7	2
all_values[4]	371	1		T1	8		T3	8		T7	2
all_values[5]	371	1		T1	8		T3	8		T7	2
all_values[6]	371	1		T1	8		T3	8		T7	2
all_values[7]	371	1		T1	8		T3	8		T7	2
all_values[8]	371	1		T1	8		T3	8		T7	2
all_values[9]	371	1		T1	8		T3	8		T7	2
all_values[10]	371	1		T1	8		T3	8		T7	2
all_values[11]	371	1		T1	8		T3	8		T7	2
all_values[12]	371	1		T1	8		T3	8		T7	2
all_values[13]	371	1		T1	8		T3	8		T7	2
all_values[14]	371	1		T1	8		T3	8		T7	2
all_values[15]	371	1		T1	8		T3	8		T7	2
all_values[16]	371	1		T1	8		T3	8		T7	2
all_values[17]	371	1		T1	8		T3	8		T7	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3841	1		T1	83		T3	84		T7	36
auto[1]	2837	1		T1	61		T3	60		T16	42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1664	1		T1	19		T3	21		T7	36
auto[1]	5014	1		T1	125		T3	123		T16	73

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	67	1		T7	2		T8	2		T17	2
all_values[0]	auto[0]	auto[1]	150	1		T1	4		T3	5		T14	5
all_values[0]	auto[1]	auto[0]	25	1		T14	1		T38	2		T55	4
all_values[0]	auto[1]	auto[1]	129	1		T1	4		T3	3		T16	5
all_values[1]	auto[0]	auto[0]	69	1		T7	2		T8	2		T17	2
all_values[1]	auto[0]	auto[1]	161	1		T1	5		T3	8		T16	2
all_values[1]	auto[1]	auto[0]	29	1		T1	1		T14	1		T38	2
all_values[1]	auto[1]	auto[1]	112	1		T1	2		T16	3		T14	4
all_values[2]	auto[0]	auto[0]	69	1		T1	1		T3	2		T7	2
all_values[2]	auto[0]	auto[1]	123	1		T1	1		T16	2		T14	7
all_values[2]	auto[1]	auto[0]	23	1		T3	2		T15	3		T38	2
all_values[2]	auto[1]	auto[1]	156	1		T1	6		T3	4		T16	3
all_values[3]	auto[0]	auto[0]	58	1		T1	2		T7	2		T8	2
all_values[3]	auto[0]	auto[1]	142	1		T3	6		T16	3		T15	4
all_values[3]	auto[1]	auto[0]	35	1		T1	2		T14	1		T57	3
all_values[3]	auto[1]	auto[1]	136	1		T1	4		T3	2		T16	2
all_values[4]	auto[0]	auto[0]	67	1		T1	2		T3	1		T7	2
all_values[4]	auto[0]	auto[1]	132	1		T1	4		T3	3		T16	5
all_values[4]	auto[1]	auto[0]	39	1		T1	1		T14	3		T38	1
all_values[4]	auto[1]	auto[1]	133	1		T1	1		T3	4		T14	3
all_values[5]	auto[0]	auto[0]	59	1		T7	2		T8	2		T17	2
all_values[5]	auto[0]	auto[1]	131	1		T1	5		T3	2		T16	5
all_values[5]	auto[1]	auto[0]	24	1		T3	1		T15	1		T55	1
all_values[5]	auto[1]	auto[1]	157	1		T1	3		T3	5		T14	7
all_values[6]	auto[0]	auto[0]	58	1		T7	2		T8	2		T17	2
all_values[6]	auto[0]	auto[1]	143	1		T1	1		T3	6		T16	5
all_values[6]	auto[1]	auto[0]	19	1		T14	1		T56	1		T58	1
all_values[6]	auto[1]	auto[1]	151	1		T1	7		T3	2		T14	2
all_values[7]	auto[0]	auto[0]	67	1		T3	1		T7	2		T8	2
all_values[7]	auto[0]	auto[1]	135	1		T1	6		T3	4		T14	1
all_values[7]	auto[1]	auto[0]	33	1		T14	2		T38	2		T59	1
all_values[7]	auto[1]	auto[1]	136	1		T1	2		T3	3		T16	3
all_values[8]	auto[0]	auto[0]	57	1		T7	2		T8	2		T17	2
all_values[8]	auto[0]	auto[1]	166	1		T1	7		T3	5		T16	4
all_values[8]	auto[1]	auto[0]	21	1		T1	1		T3	1		T14	1
all_values[8]	auto[1]	auto[1]	127	1		T3	2		T16	1		T15	4
all_values[9]	auto[0]	auto[0]	71	1		T3	1		T7	2		T8	2
all_values[9]	auto[0]	auto[1]	151	1		T1	6		T3	3		T14	4
all_values[9]	auto[1]	auto[0]	28	1		T1	1		T16	5		T38	2
all_values[9]	auto[1]	auto[1]	121	1		T1	1		T3	4		T14	4
all_values[10]	auto[0]	auto[0]	66	1		T7	2		T8	2		T17	2
all_values[10]	auto[0]	auto[1]	159	1		T1	7		T3	7		T16	5
all_values[10]	auto[1]	auto[0]	13	1		T38	1		T55	1		T60	3
all_values[10]	auto[1]	auto[1]	133	1		T1	1		T3	1		T14	6
all_values[11]	auto[0]	auto[0]	78	1		T7	2		T8	2		T16	2
all_values[11]	auto[0]	auto[1]	145	1		T1	1		T3	3		T16	3
all_values[11]	auto[1]	auto[0]	19	1		T14	1		T55	4		T61	1
all_values[11]	auto[1]	auto[1]	129	1		T1	7		T3	5		T14	1
all_values[12]	auto[0]	auto[0]	70	1		T3	1		T7	2		T8	2
all_values[12]	auto[0]	auto[1]	171	1		T1	5		T3	5		T14	4
all_values[12]	auto[1]	auto[0]	22	1		T16	3		T14	1		T55	1
all_values[12]	auto[1]	auto[1]	108	1		T1	3		T3	2		T14	3
all_values[13]	auto[0]	auto[0]	67	1		T1	1		T7	2		T8	2
all_values[13]	auto[0]	auto[1]	163	1		T1	6		T3	5		T16	4
all_values[13]	auto[1]	auto[0]	26	1		T3	1		T38	1		T60	3
all_values[13]	auto[1]	auto[1]	115	1		T1	1		T3	2		T16	1
all_values[14]	auto[0]	auto[0]	74	1		T1	1		T7	2		T8	2
all_values[14]	auto[0]	auto[1]	150	1		T1	3		T3	5		T14	6
all_values[14]	auto[1]	auto[0]	24	1		T1	2		T3	1		T16	1
all_values[14]	auto[1]	auto[1]	123	1		T1	2		T3	2		T16	4
all_values[15]	auto[0]	auto[0]	72	1		T3	1		T7	2		T8	2
all_values[15]	auto[0]	auto[1]	135	1		T1	5		T3	3		T16	4
all_values[15]	auto[1]	auto[0]	24	1		T3	1		T16	1		T59	2
all_values[15]	auto[1]	auto[1]	140	1		T1	3		T3	3		T14	3
all_values[16]	auto[0]	auto[0]	77	1		T3	3		T7	2		T8	2
all_values[16]	auto[0]	auto[1]	144	1		T1	4		T14	6		T38	5
all_values[16]	auto[1]	auto[0]	23	1		T3	2		T16	1		T38	1
all_values[16]	auto[1]	auto[1]	127	1		T1	4		T3	3		T16	4
all_values[17]	auto[0]	auto[0]	59	1		T1	2		T3	1		T7	2
all_values[17]	auto[0]	auto[1]	135	1		T1	4		T3	3		T14	5
all_values[17]	auto[1]	auto[0]	32	1		T1	2		T3	1		T14	1
all_values[17]	auto[1]	auto[1]	145	1		T3	3		T16	5		T14	2