| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 67.93 | 65.32 | 59.60 | 86.78 | 0.00 | 69.84 | 97.77 | 96.22 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 56.00 | 56.00 | 62.19 | 62.19 | 51.41 | 51.41 | 88.50 | 88.50 | 0.00 | 0.00 | 63.33 | 63.33 | 91.62 | 91.62 | 34.95 | 34.95 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2644314739 |
| 63.15 | 7.15 | 62.89 | 0.70 | 52.57 | 1.16 | 92.02 | 3.52 | 0.00 | 0.00 | 63.33 | 0.00 | 91.62 | 0.00 | 79.64 | 44.68 | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1735528410 |
| 65.71 | 2.56 | 65.32 | 2.42 | 58.27 | 5.70 | 93.43 | 1.41 | 0.00 | 0.00 | 69.76 | 6.43 | 93.58 | 1.96 | 79.64 | 0.00 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3871336849 |
| 66.91 | 1.20 | 65.32 | 0.00 | 58.27 | 0.00 | 93.90 | 0.47 | 0.00 | 0.00 | 69.76 | 0.00 | 93.58 | 0.00 | 87.57 | 7.93 | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.735401852 |
| 67.78 | 0.87 | 65.32 | 0.00 | 59.27 | 1.00 | 93.90 | 0.00 | 0.00 | 0.00 | 69.84 | 0.08 | 94.97 | 1.40 | 91.17 | 3.60 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.168386172 |
| 68.21 | 0.42 | 65.32 | 0.00 | 59.27 | 0.00 | 93.90 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 2.79 | 91.35 | 0.18 | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.599871782 |
| 68.62 | 0.41 | 65.32 | 0.00 | 59.27 | 0.00 | 93.90 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 94.23 | 2.88 | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1476844793 |
| 68.79 | 0.17 | 65.32 | 0.00 | 59.27 | 0.00 | 95.07 | 1.17 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 94.23 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2979080079 |
| 68.91 | 0.13 | 65.32 | 0.00 | 59.27 | 0.00 | 95.07 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 95.14 | 0.90 | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.745644834 |
| 68.99 | 0.08 | 65.32 | 0.00 | 59.27 | 0.00 | 95.07 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 95.68 | 0.54 | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.127921466 |
| 69.06 | 0.07 | 65.32 | 0.00 | 59.27 | 0.00 | 95.54 | 0.47 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 95.68 | 0.00 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2887965069 |
| 69.11 | 0.05 | 65.32 | 0.00 | 59.27 | 0.00 | 95.54 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.04 | 0.36 | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2706105891 |
| 69.14 | 0.03 | 65.32 | 0.00 | 59.46 | 0.19 | 95.54 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.04 | 0.00 | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3221654948 |
| 69.16 | 0.03 | 65.32 | 0.00 | 59.46 | 0.00 | 95.54 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.22 | 0.18 | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3225495412 |
| 69.18 | 0.01 | 65.32 | 0.00 | 59.55 | 0.09 | 95.54 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3040186390 |
| 69.18 | 0.01 | 65.32 | 0.00 | 59.58 | 0.02 | 95.54 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2338769892 |
| 69.18 | 0.01 | 65.32 | 0.00 | 59.60 | 0.02 | 95.54 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3329508980 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3106906464 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2245357286 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1525778420 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1326657884 |
| /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3842204124 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3015361890 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3259604548 |
| /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4152750495 |
| /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3240099221 |
| /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.895756973 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.63832958 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2530713098 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.144347038 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3997216755 |
| /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4259027548 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3999826972 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2983180054 |
| /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3808957694 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2788864869 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1028555198 |
| /workspace/coverage/cover_reg_top/10.usbdev_intr_test.894454228 |
| /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1541084148 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2870114773 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1794482985 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1247179156 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3913352913 |
| /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.734874347 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2689863411 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.982424840 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2437719526 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4240643032 |
| /workspace/coverage/cover_reg_top/12.usbdev_intr_test.536281685 |
| /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.275324929 |
| /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.212288650 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3994325759 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1631300523 |
| /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3178627607 |
| /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4262226622 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2329555594 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.763513035 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2561292733 |
| /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1035006530 |
| /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.47018826 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2305435949 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3692545794 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1960342676 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3214758594 |
| /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2591101367 |
| /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3390205029 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.540571209 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.879651977 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.451046544 |
| /workspace/coverage/cover_reg_top/16.usbdev_intr_test.37963920 |
| /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.121089940 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3492388165 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1961643882 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2301055456 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3591675596 |
| /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2704642845 |
| /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3377807943 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2942270151 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1938311828 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.395930115 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1281366109 |
| /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3346729184 |
| /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1137518247 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3802752163 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2863657345 |
| /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2391936781 |
| /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.927988181 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3308427602 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1219622610 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1345456554 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1198896430 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4156384371 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1988200507 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.405316409 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4231982995 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1141681861 |
| /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.997257361 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2442448627 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.685383911 |
| /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1874417855 |
| /workspace/coverage/cover_reg_top/22.usbdev_intr_test.919431574 |
| /workspace/coverage/cover_reg_top/23.usbdev_intr_test.930839586 |
| /workspace/coverage/cover_reg_top/24.usbdev_intr_test.484103856 |
| /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2885065403 |
| /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2677124970 |
| /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4134336054 |
| /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1973147021 |
| /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3915736441 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3484930238 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3577159859 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2206762718 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2058315224 |
| /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4000790293 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2401364189 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2957203965 |
| /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.793044855 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1342451737 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2328336946 |
| /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1072065081 |
| /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3902600680 |
| /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2842979478 |
| /workspace/coverage/cover_reg_top/33.usbdev_intr_test.107843544 |
| /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3945101846 |
| /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1495834981 |
| /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2478242856 |
| /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1856031403 |
| /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4066097486 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1782110822 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3408968198 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2021724850 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.460718650 |
| /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4282696840 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2062588948 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1056982097 |
| /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.522268753 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.625797715 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2865291115 |
| /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3323444269 |
| /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2542611201 |
| /workspace/coverage/cover_reg_top/42.usbdev_intr_test.707388071 |
| /workspace/coverage/cover_reg_top/43.usbdev_intr_test.566115240 |
| /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2602836491 |
| /workspace/coverage/cover_reg_top/45.usbdev_intr_test.856687590 |
| /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2571845893 |
| /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1071092045 |
| /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1585572168 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3787294310 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2449293462 |
| /workspace/coverage/cover_reg_top/5.usbdev_intr_test.204453522 |
| /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2589197538 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1107520666 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1335498127 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2630612746 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3771938602 |
| /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3676412968 |
| /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2813400553 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.736352725 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2342374921 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.369838891 |
| /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1061470461 |
| /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1547444424 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2901477946 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2566725020 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.753725239 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1469244694 |
| /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1315162242 |
| /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1545270903 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.238954338 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.903785947 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3897522470 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1997481701 |
| /workspace/coverage/cover_reg_top/9.usbdev_intr_test.731841868 |
| /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2313533167 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4013660212 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.11898872 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2591101367 | Jul 01 04:47:34 PM PDT 24 | Jul 01 04:47:37 PM PDT 24 | 81540844 ps | ||
| T2 | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3577159859 | Jul 01 04:47:20 PM PDT 24 | Jul 01 04:47:30 PM PDT 24 | 173576191 ps | ||
| T3 | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2677124970 | Jul 01 04:47:41 PM PDT 24 | Jul 01 04:47:46 PM PDT 24 | 54879071 ps | ||
| T7 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.168386172 | Jul 01 04:47:32 PM PDT 24 | Jul 01 04:47:38 PM PDT 24 | 313137338 ps | ||
| T4 | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.753725239 | Jul 01 04:47:24 PM PDT 24 | Jul 01 04:47:30 PM PDT 24 | 101289002 ps | ||
| T5 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3871336849 | Jul 01 04:47:24 PM PDT 24 | Jul 01 04:47:29 PM PDT 24 | 80172029 ps | ||
| T9 | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1345456554 | Jul 01 04:47:14 PM PDT 24 | Jul 01 04:47:24 PM PDT 24 | 125107096 ps | ||
| T8 | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2442448627 | Jul 01 04:47:16 PM PDT 24 | Jul 01 04:47:25 PM PDT 24 | 120528049 ps | ||
| T16 | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1585572168 | Jul 01 04:47:51 PM PDT 24 | Jul 01 04:47:57 PM PDT 24 | 41218748 ps | ||
| T6 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2644314739 | Jul 01 04:47:24 PM PDT 24 | Jul 01 04:47:33 PM PDT 24 | 830314978 ps | ||
| T24 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.47018826 | Jul 01 04:47:36 PM PDT 24 | Jul 01 04:47:41 PM PDT 24 | 212285539 ps | ||
| T25 | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.599871782 | Jul 01 04:47:41 PM PDT 24 | Jul 01 04:47:46 PM PDT 24 | 117439781 ps | ||
| T17 | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2689863411 | Jul 01 04:47:33 PM PDT 24 | Jul 01 04:47:37 PM PDT 24 | 188444066 ps | ||
| T37 | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1198896430 | Jul 01 04:47:15 PM PDT 24 | Jul 01 04:47:29 PM PDT 24 | 1468976617 ps | ||
| T18 | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3802752163 | Jul 01 04:47:42 PM PDT 24 | Jul 01 04:47:50 PM PDT 24 | 117662486 ps | ||
| T14 | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1476844793 | Jul 01 04:47:16 PM PDT 24 | Jul 01 04:47:24 PM PDT 24 | 42196646 ps | ||
| T15 | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4000790293 | Jul 01 04:47:22 PM PDT 24 | Jul 01 04:47:28 PM PDT 24 | 85685155 ps | ||
| T38 | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1735528410 | Jul 01 04:47:48 PM PDT 24 | Jul 01 04:47:54 PM PDT 24 | 53850151 ps | ||
| T19 | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.879651977 | Jul 01 04:47:42 PM PDT 24 | Jul 01 04:47:49 PM PDT 24 | 117775194 ps | ||
| T39 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3040186390 | Jul 01 04:47:15 PM PDT 24 | Jul 01 04:47:32 PM PDT 24 | 1872347505 ps | ||
| T40 | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2589197538 | Jul 01 04:47:22 PM PDT 24 | Jul 01 04:47:29 PM PDT 24 | 158656922 ps | ||
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| T41 | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4262226622 | Jul 01 04:47:34 PM PDT 24 | Jul 01 04:47:38 PM PDT 24 | 268856807 ps | ||
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| T78 | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1541084148 | Jul 01 04:47:33 PM PDT 24 | Jul 01 04:47:37 PM PDT 24 | 86864823 ps | ||
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| T144 | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.405316409 | Jul 01 04:47:17 PM PDT 24 | Jul 01 04:47:24 PM PDT 24 | 54934711 ps | ||
| T145 | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3408968198 | Jul 01 04:47:26 PM PDT 24 | Jul 01 04:47:35 PM PDT 24 | 615090644 ps | ||
| T146 | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2885065403 | Jul 01 04:47:40 PM PDT 24 | Jul 01 04:47:43 PM PDT 24 | 44638361 ps | ||
| T147 | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1525778420 | Jul 01 04:47:14 PM PDT 24 | Jul 01 04:47:22 PM PDT 24 | 67276964 ps | ||
| T148 | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1107520666 | Jul 01 04:47:22 PM PDT 24 | Jul 01 04:47:29 PM PDT 24 | 124860783 ps | ||
| T149 | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.731841868 | Jul 01 04:47:34 PM PDT 24 | Jul 01 04:47:38 PM PDT 24 | 49601798 ps | ||
| T150 | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4240643032 | Jul 01 04:47:36 PM PDT 24 | Jul 01 04:47:40 PM PDT 24 | 115662300 ps | ||
| T151 | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3913352913 | Jul 01 04:47:32 PM PDT 24 | Jul 01 04:47:35 PM PDT 24 | 42551807 ps | ||
| T152 | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3676412968 | Jul 01 04:47:22 PM PDT 24 | Jul 01 04:47:28 PM PDT 24 | 75628132 ps | ||
| T12 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2530713098 | Jul 01 04:47:16 PM PDT 24 | Jul 01 04:47:24 PM PDT 24 | 60177022 ps | ||
| T153 | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3259604548 | Jul 01 04:47:15 PM PDT 24 | Jul 01 04:47:24 PM PDT 24 | 384606792 ps | ||
| T154 | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.927988181 | Jul 01 04:47:46 PM PDT 24 | Jul 01 04:47:54 PM PDT 24 | 151985925 ps | ||
| T155 | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.127921466 | Jul 01 04:47:40 PM PDT 24 | Jul 01 04:47:46 PM PDT 24 | 541346156 ps | ||
| T156 | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.685383911 | Jul 01 04:47:15 PM PDT 24 | Jul 01 04:47:24 PM PDT 24 | 365561353 ps | ||
| T157 | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2863657345 | Jul 01 04:47:43 PM PDT 24 | Jul 01 04:47:50 PM PDT 24 | 93002692 ps | ||
| T158 | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2437719526 | Jul 01 04:47:30 PM PDT 24 | Jul 01 04:47:34 PM PDT 24 | 326052036 ps | ||
| T159 | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3178627607 | Jul 01 04:47:36 PM PDT 24 | Jul 01 04:47:39 PM PDT 24 | 66687490 ps | ||
| T160 | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3999826972 | Jul 01 04:47:15 PM PDT 24 | Jul 01 04:47:23 PM PDT 24 | 49956939 ps | ||
| T161 | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.484103856 | Jul 01 04:47:45 PM PDT 24 | Jul 01 04:47:51 PM PDT 24 | 43065180 ps | ||
| T162 | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.204453522 | Jul 01 04:47:24 PM PDT 24 | Jul 01 04:47:30 PM PDT 24 | 36304303 ps | ||
| T163 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3692545794 | Jul 01 04:47:40 PM PDT 24 | Jul 01 04:47:46 PM PDT 24 | 988690656 ps | ||
| T164 | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3214758594 | Jul 01 04:47:36 PM PDT 24 | Jul 01 04:47:40 PM PDT 24 | 69752142 ps | ||
| T165 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.625797715 | Jul 01 04:47:24 PM PDT 24 | Jul 01 04:47:31 PM PDT 24 | 168078463 ps | ||
| T166 | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.63832958 | Jul 01 04:47:14 PM PDT 24 | Jul 01 04:47:24 PM PDT 24 | 290252920 ps | ||
| T167 | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3945101846 | Jul 01 04:47:41 PM PDT 24 | Jul 01 04:47:45 PM PDT 24 | 36137110 ps | ||
| T168 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1938311828 | Jul 01 04:47:40 PM PDT 24 | Jul 01 04:47:47 PM PDT 24 | 351426162 ps | ||
| T169 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3240099221 | Jul 01 04:47:16 PM PDT 24 | Jul 01 04:47:24 PM PDT 24 | 48106319 ps | ||
| T170 | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3484930238 | Jul 01 04:47:20 PM PDT 24 | Jul 01 04:47:29 PM PDT 24 | 79153015 ps | ||
| T171 | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3323444269 | Jul 01 04:47:40 PM PDT 24 | Jul 01 04:47:43 PM PDT 24 | 46483491 ps | ||
| T172 | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2058315224 | Jul 01 04:47:20 PM PDT 24 | Jul 01 04:47:27 PM PDT 24 | 59421197 ps | ||
| T173 | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.37963920 | Jul 01 04:47:43 PM PDT 24 | Jul 01 04:47:49 PM PDT 24 | 66235177 ps | ||
| T174 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.982424840 | Jul 01 04:47:36 PM PDT 24 | Jul 01 04:47:45 PM PDT 24 | 1406759247 ps | ||
| T175 | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2571845893 | Jul 01 04:47:41 PM PDT 24 | Jul 01 04:47:45 PM PDT 24 | 39382450 ps |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2644314739 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 830314978 ps |
| CPU time | 4.4 seconds |
| Started | Jul 01 04:47:24 PM PDT 24 |
| Finished | Jul 01 04:47:33 PM PDT 24 |
| Peak memory | 206036 kb |
| Host | smart-c4cd34aa-9bd2-43a4-ac84-3654c98ef4b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2644314739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2644314739 |
| Directory | /workspace/6.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1735528410 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 53850151 ps |
| CPU time | 0.73 seconds |
| Started | Jul 01 04:47:48 PM PDT 24 |
| Finished | Jul 01 04:47:54 PM PDT 24 |
| Peak memory | 205828 kb |
| Host | smart-8d08ad11-cfac-46d3-a3a6-fa659198acc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1735528410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1735528410 |
| Directory | /workspace/48.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3871336849 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 80172029 ps |
| CPU time | 0.81 seconds |
| Started | Jul 01 04:47:24 PM PDT 24 |
| Finished | Jul 01 04:47:29 PM PDT 24 |
| Peak memory | 205912 kb |
| Host | smart-8e38fa46-ab71-487c-8592-529a5e62590f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3871336849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3871336849 |
| Directory | /workspace/3.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.735401852 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 52134092 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 205900 kb |
| Host | smart-3c23334c-30b1-45a7-af89-45c1b5bf8bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=735401852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.735401852 |
| Directory | /workspace/39.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.168386172 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 313137338 ps |
| CPU time | 2.94 seconds |
| Started | Jul 01 04:47:32 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 214324 kb |
| Host | smart-56874baa-a3f3-41af-9c40-fd970a9cfcf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=168386172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.168386172 |
| Directory | /workspace/12.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.599871782 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 117439781 ps |
| CPU time | 0.95 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 205888 kb |
| Host | smart-f65e918d-885a-4857-8874-bbfba5931db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=599871782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.599871782 |
| Directory | /workspace/19.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1476844793 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 42196646 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 205780 kb |
| Host | smart-8f87adef-dcc4-4890-9f2e-8affcc2f932b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1476844793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1476844793 |
| Directory | /workspace/2.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2979080079 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 60763056 ps |
| CPU time | 0.86 seconds |
| Started | Jul 01 04:47:18 PM PDT 24 |
| Finished | Jul 01 04:47:25 PM PDT 24 |
| Peak memory | 205880 kb |
| Host | smart-8a4d7a7a-8d01-40a2-9c17-295160fecdfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2979080079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2979080079 |
| Directory | /workspace/0.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.745644834 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 82255456 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:44 PM PDT 24 |
| Finished | Jul 01 04:47:50 PM PDT 24 |
| Peak memory | 205804 kb |
| Host | smart-3693275a-6d92-4e6b-9a57-9fd64e203842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=745644834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.745644834 |
| Directory | /workspace/21.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.127921466 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 541346156 ps |
| CPU time | 2.83 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 205976 kb |
| Host | smart-5617921a-3135-4c81-bcf8-18bfd06ac701 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=127921466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.127921466 |
| Directory | /workspace/18.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2887965069 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 55466849 ps |
| CPU time | 0.79 seconds |
| Started | Jul 01 04:47:21 PM PDT 24 |
| Finished | Jul 01 04:47:28 PM PDT 24 |
| Peak memory | 205896 kb |
| Host | smart-c8dd1748-1df2-4a3a-831d-ac14e192832f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2887965069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2887965069 |
| Directory | /workspace/4.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2706105891 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 832637354 ps |
| CPU time | 4.91 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:42 PM PDT 24 |
| Peak memory | 205864 kb |
| Host | smart-8853ec51-b5af-40a6-a62e-9c73b922de7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2706105891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2706105891 |
| Directory | /workspace/15.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3221654948 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 251758746 ps |
| CPU time | 2.82 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 222184 kb |
| Host | smart-4b2de407-0223-4ff6-bce6-0cb8c57baa75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3221654948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3221654948 |
| Directory | /workspace/13.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3225495412 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 101063301 ps |
| CPU time | 0.73 seconds |
| Started | Jul 01 04:47:33 PM PDT 24 |
| Finished | Jul 01 04:47:37 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-7fd66906-ae4f-43f2-b9ff-f73896c01cda |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3225495412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3225495412 |
| Directory | /workspace/11.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3040186390 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1872347505 ps |
| CPU time | 9.48 seconds |
| Started | Jul 01 04:47:15 PM PDT 24 |
| Finished | Jul 01 04:47:32 PM PDT 24 |
| Peak memory | 205964 kb |
| Host | smart-f68f50d5-e1cc-497b-b39a-09e4d8429798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3040186390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3040186390 |
| Directory | /workspace/1.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2338769892 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 303233067 ps |
| CPU time | 3.11 seconds |
| Started | Jul 01 04:47:14 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 222180 kb |
| Host | smart-a9ec0efc-db87-4aa0-bbd6-b731188f84d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2338769892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2338769892 |
| Directory | /workspace/1.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3329508980 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 270931034 ps |
| CPU time | 2.39 seconds |
| Started | Jul 01 04:47:15 PM PDT 24 |
| Finished | Jul 01 04:47:23 PM PDT 24 |
| Peak memory | 206036 kb |
| Host | smart-cae78d29-13e8-4b3e-8149-f8c731a18494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3329508980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3329508980 |
| Directory | /workspace/1.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3106906464 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 297921087 ps |
| CPU time | 3.54 seconds |
| Started | Jul 01 04:47:14 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 206044 kb |
| Host | smart-85c84bda-14d8-4c15-a8af-c4a1f2800472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3106906464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3106906464 |
| Directory | /workspace/0.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2245357286 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1684749772 ps |
| CPU time | 8.87 seconds |
| Started | Jul 01 04:47:19 PM PDT 24 |
| Finished | Jul 01 04:47:34 PM PDT 24 |
| Peak memory | 205992 kb |
| Host | smart-44732bd7-76c4-42cd-a19c-19d8b85dd93e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2245357286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2245357286 |
| Directory | /workspace/0.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1525778420 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 67276964 ps |
| CPU time | 1.62 seconds |
| Started | Jul 01 04:47:14 PM PDT 24 |
| Finished | Jul 01 04:47:22 PM PDT 24 |
| Peak memory | 214220 kb |
| Host | smart-1a94d19e-9260-44f7-bb78-a7a252aeff8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525778420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde v_csr_mem_rw_with_rand_reset.1525778420 |
| Directory | /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1326657884 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 66771440 ps |
| CPU time | 1 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 205964 kb |
| Host | smart-3c3b0a18-b08b-408b-9150-e9378f40aaff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1326657884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1326657884 |
| Directory | /workspace/0.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3842204124 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 44538003 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 04:47:15 PM PDT 24 |
| Finished | Jul 01 04:47:22 PM PDT 24 |
| Peak memory | 205792 kb |
| Host | smart-6fc0e3d0-61f9-48e1-a43c-e2fb44dd2677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3842204124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3842204124 |
| Directory | /workspace/0.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3015361890 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 149856991 ps |
| CPU time | 1.5 seconds |
| Started | Jul 01 04:47:15 PM PDT 24 |
| Finished | Jul 01 04:47:23 PM PDT 24 |
| Peak memory | 214132 kb |
| Host | smart-39a5ce36-bf44-4967-b35d-84a31c7c52d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3015361890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3015361890 |
| Directory | /workspace/0.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3259604548 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 384606792 ps |
| CPU time | 2.66 seconds |
| Started | Jul 01 04:47:15 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 205944 kb |
| Host | smart-e232c8ee-53c5-413e-a3d3-fc363889c49c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3259604548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3259604548 |
| Directory | /workspace/0.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4152750495 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 333896937 ps |
| CPU time | 1.74 seconds |
| Started | Jul 01 04:47:14 PM PDT 24 |
| Finished | Jul 01 04:47:22 PM PDT 24 |
| Peak memory | 205960 kb |
| Host | smart-7c8eaabb-9413-4927-9f1f-3a0a8c23ab29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4152750495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.4152750495 |
| Directory | /workspace/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3240099221 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 48106319 ps |
| CPU time | 1.23 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 214264 kb |
| Host | smart-5e6b2298-e928-4bc4-8eb3-0a7b0bbeaf89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3240099221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3240099221 |
| Directory | /workspace/0.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.895756973 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 460343477 ps |
| CPU time | 2.95 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:26 PM PDT 24 |
| Peak memory | 206036 kb |
| Host | smart-26a92080-21d7-4cd2-b8fa-ae899ef382a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=895756973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.895756973 |
| Directory | /workspace/0.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.63832958 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 290252920 ps |
| CPU time | 3.53 seconds |
| Started | Jul 01 04:47:14 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 205952 kb |
| Host | smart-e7f4b40a-fd36-4226-a49d-b47be7031111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=63832958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.63832958 |
| Directory | /workspace/1.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2530713098 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 60177022 ps |
| CPU time | 0.79 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 205880 kb |
| Host | smart-4798fd49-8eb1-4774-b40c-06746803b904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2530713098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2530713098 |
| Directory | /workspace/1.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.144347038 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 104400048 ps |
| CPU time | 2.01 seconds |
| Started | Jul 01 04:47:14 PM PDT 24 |
| Finished | Jul 01 04:47:22 PM PDT 24 |
| Peak memory | 214228 kb |
| Host | smart-b94a313e-08b7-451d-9dbb-066c6d08ce47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144347038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev _csr_mem_rw_with_rand_reset.144347038 |
| Directory | /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3997216755 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 78035425 ps |
| CPU time | 1.02 seconds |
| Started | Jul 01 04:47:15 PM PDT 24 |
| Finished | Jul 01 04:47:22 PM PDT 24 |
| Peak memory | 205984 kb |
| Host | smart-63da97fb-2ff7-4a18-b173-df917e202507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3997216755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3997216755 |
| Directory | /workspace/1.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4259027548 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 103956920 ps |
| CPU time | 0.71 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-d0dab5e6-c1fd-4e63-825c-5f123cf9cdc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4259027548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.4259027548 |
| Directory | /workspace/1.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3999826972 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 49956939 ps |
| CPU time | 1.41 seconds |
| Started | Jul 01 04:47:15 PM PDT 24 |
| Finished | Jul 01 04:47:23 PM PDT 24 |
| Peak memory | 214164 kb |
| Host | smart-9ee7840b-e3ac-4ade-bc2a-45e73a20a2da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3999826972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3999826972 |
| Directory | /workspace/1.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2983180054 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 255935082 ps |
| CPU time | 2.56 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:25 PM PDT 24 |
| Peak memory | 205924 kb |
| Host | smart-df23f9cb-ba9f-431e-85e8-bbff6f5168fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2983180054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2983180054 |
| Directory | /workspace/1.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3808957694 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 192766199 ps |
| CPU time | 1.65 seconds |
| Started | Jul 01 04:47:12 PM PDT 24 |
| Finished | Jul 01 04:47:20 PM PDT 24 |
| Peak memory | 206032 kb |
| Host | smart-482e39be-423e-4c48-b749-be483183e720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3808957694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3808957694 |
| Directory | /workspace/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2788864869 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 214328220 ps |
| CPU time | 2 seconds |
| Started | Jul 01 04:47:37 PM PDT 24 |
| Finished | Jul 01 04:47:42 PM PDT 24 |
| Peak memory | 218816 kb |
| Host | smart-64948d51-bddf-4965-afef-bc7873a67302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788864869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd ev_csr_mem_rw_with_rand_reset.2788864869 |
| Directory | /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1028555198 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 40427446 ps |
| CPU time | 0.85 seconds |
| Started | Jul 01 04:47:32 PM PDT 24 |
| Finished | Jul 01 04:47:34 PM PDT 24 |
| Peak memory | 205896 kb |
| Host | smart-2d306546-fe02-4324-88ee-bbcd1500b8c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1028555198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1028555198 |
| Directory | /workspace/10.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.894454228 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 48346839 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 04:47:31 PM PDT 24 |
| Finished | Jul 01 04:47:34 PM PDT 24 |
| Peak memory | 205824 kb |
| Host | smart-d1a35b01-101e-4545-8e6f-bd6aca67e4f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=894454228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.894454228 |
| Directory | /workspace/10.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1541084148 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 86864823 ps |
| CPU time | 1.1 seconds |
| Started | Jul 01 04:47:33 PM PDT 24 |
| Finished | Jul 01 04:47:37 PM PDT 24 |
| Peak memory | 206088 kb |
| Host | smart-cb884932-91e6-4677-ab29-80b4b25f5f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1541084148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1541084148 |
| Directory | /workspace/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2870114773 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 209436865 ps |
| CPU time | 2.48 seconds |
| Started | Jul 01 04:47:32 PM PDT 24 |
| Finished | Jul 01 04:47:37 PM PDT 24 |
| Peak memory | 206120 kb |
| Host | smart-6cc9319d-a34e-4ab2-ad1c-00a71c2654a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2870114773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2870114773 |
| Directory | /workspace/10.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1794482985 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 781933634 ps |
| CPU time | 5.14 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:47 PM PDT 24 |
| Peak memory | 206000 kb |
| Host | smart-098963d1-88b1-4886-8c37-951f7b082271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1794482985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1794482985 |
| Directory | /workspace/10.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1247179156 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 167921433 ps |
| CPU time | 1.87 seconds |
| Started | Jul 01 04:47:33 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 214400 kb |
| Host | smart-4a62b828-a40d-4dcf-9eea-5c76ed502f3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247179156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.1247179156 |
| Directory | /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3913352913 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 42551807 ps |
| CPU time | 0.83 seconds |
| Started | Jul 01 04:47:32 PM PDT 24 |
| Finished | Jul 01 04:47:35 PM PDT 24 |
| Peak memory | 205872 kb |
| Host | smart-cb9d2e28-2a6e-4fdd-bd67-b70d78287caf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3913352913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3913352913 |
| Directory | /workspace/11.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.734874347 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 106125513 ps |
| CPU time | 1.1 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 205852 kb |
| Host | smart-6230dde0-3ac9-4a69-868d-89a5042c817d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=734874347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.734874347 |
| Directory | /workspace/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2689863411 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 188444066 ps |
| CPU time | 1.66 seconds |
| Started | Jul 01 04:47:33 PM PDT 24 |
| Finished | Jul 01 04:47:37 PM PDT 24 |
| Peak memory | 214364 kb |
| Host | smart-1d4ff146-d855-4c59-8c28-8be2766efa6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2689863411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2689863411 |
| Directory | /workspace/11.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.982424840 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1406759247 ps |
| CPU time | 5.8 seconds |
| Started | Jul 01 04:47:36 PM PDT 24 |
| Finished | Jul 01 04:47:45 PM PDT 24 |
| Peak memory | 206068 kb |
| Host | smart-5ff82047-f80d-469e-b754-8ee61b9cbe69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=982424840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.982424840 |
| Directory | /workspace/11.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2437719526 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 326052036 ps |
| CPU time | 1.91 seconds |
| Started | Jul 01 04:47:30 PM PDT 24 |
| Finished | Jul 01 04:47:34 PM PDT 24 |
| Peak memory | 214168 kb |
| Host | smart-44e34420-a934-4e63-9b9c-dcf06b080bc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437719526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd ev_csr_mem_rw_with_rand_reset.2437719526 |
| Directory | /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4240643032 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 115662300 ps |
| CPU time | 1.04 seconds |
| Started | Jul 01 04:47:36 PM PDT 24 |
| Finished | Jul 01 04:47:40 PM PDT 24 |
| Peak memory | 205972 kb |
| Host | smart-c96ca25c-2eed-4bb5-a382-0276a4d35b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4240643032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4240643032 |
| Directory | /workspace/12.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.536281685 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 49841080 ps |
| CPU time | 0.73 seconds |
| Started | Jul 01 04:47:36 PM PDT 24 |
| Finished | Jul 01 04:47:40 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-05ba6613-396f-4bd2-901f-3fb049ca0472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=536281685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.536281685 |
| Directory | /workspace/12.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.275324929 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 139822683 ps |
| CPU time | 1.22 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 206024 kb |
| Host | smart-adc3cacb-115c-4af9-b996-d3f4efef45d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=275324929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.275324929 |
| Directory | /workspace/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.212288650 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1077551954 ps |
| CPU time | 5.56 seconds |
| Started | Jul 01 04:47:33 PM PDT 24 |
| Finished | Jul 01 04:47:41 PM PDT 24 |
| Peak memory | 206192 kb |
| Host | smart-397e8124-457d-4db5-b9bb-9753d1eb49cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=212288650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.212288650 |
| Directory | /workspace/12.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3994325759 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 192233764 ps |
| CPU time | 1.82 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:39 PM PDT 24 |
| Peak memory | 214208 kb |
| Host | smart-26ca3563-ead5-4079-9ebe-38839ec3877b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994325759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.3994325759 |
| Directory | /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1631300523 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 94487971 ps |
| CPU time | 1.06 seconds |
| Started | Jul 01 04:47:35 PM PDT 24 |
| Finished | Jul 01 04:47:39 PM PDT 24 |
| Peak memory | 205972 kb |
| Host | smart-529757fb-1f76-404e-aaf5-e692de204abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1631300523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1631300523 |
| Directory | /workspace/13.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3178627607 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 66687490 ps |
| CPU time | 0.71 seconds |
| Started | Jul 01 04:47:36 PM PDT 24 |
| Finished | Jul 01 04:47:39 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-b3891044-ce83-4b40-b2e4-50a26589cef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3178627607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3178627607 |
| Directory | /workspace/13.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4262226622 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 268856807 ps |
| CPU time | 1.25 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 205968 kb |
| Host | smart-5f8e22f1-05f9-43b3-88f6-c36d0d5b288c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4262226622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.4262226622 |
| Directory | /workspace/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2329555594 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1052781200 ps |
| CPU time | 3.48 seconds |
| Started | Jul 01 04:47:32 PM PDT 24 |
| Finished | Jul 01 04:47:37 PM PDT 24 |
| Peak memory | 206024 kb |
| Host | smart-bd0c4c52-9ea4-455e-847d-49c6c996caa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2329555594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2329555594 |
| Directory | /workspace/13.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.763513035 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 184793907 ps |
| CPU time | 1.98 seconds |
| Started | Jul 01 04:47:33 PM PDT 24 |
| Finished | Jul 01 04:47:37 PM PDT 24 |
| Peak memory | 214308 kb |
| Host | smart-fd3bf954-aff0-4d72-aced-61ae00bff8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763513035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde v_csr_mem_rw_with_rand_reset.763513035 |
| Directory | /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2561292733 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 111179859 ps |
| CPU time | 1.1 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 205596 kb |
| Host | smart-0c85c8f9-ef7d-4d09-bc06-606f49f8914e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2561292733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2561292733 |
| Directory | /workspace/14.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1035006530 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 32470049 ps |
| CPU time | 0.66 seconds |
| Started | Jul 01 04:47:32 PM PDT 24 |
| Finished | Jul 01 04:47:34 PM PDT 24 |
| Peak memory | 205816 kb |
| Host | smart-f5d41248-48fc-4f99-9319-1145c72cb480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1035006530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1035006530 |
| Directory | /workspace/14.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.47018826 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 212285539 ps |
| CPU time | 1.84 seconds |
| Started | Jul 01 04:47:36 PM PDT 24 |
| Finished | Jul 01 04:47:41 PM PDT 24 |
| Peak memory | 205968 kb |
| Host | smart-c93b8cb8-e4b5-4ceb-87ab-e6f311b2060b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=47018826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.47018826 |
| Directory | /workspace/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2305435949 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 370178676 ps |
| CPU time | 3.54 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:40 PM PDT 24 |
| Peak memory | 222396 kb |
| Host | smart-9f9d7fc4-b60b-445e-a639-52bb34001e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2305435949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2305435949 |
| Directory | /workspace/14.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3692545794 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 988690656 ps |
| CPU time | 3.59 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 205972 kb |
| Host | smart-34ced63e-4cb7-4f5d-958e-3db5ab2f3adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3692545794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3692545794 |
| Directory | /workspace/14.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1960342676 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 121940520 ps |
| CPU time | 1.22 seconds |
| Started | Jul 01 04:47:32 PM PDT 24 |
| Finished | Jul 01 04:47:35 PM PDT 24 |
| Peak memory | 214216 kb |
| Host | smart-ad8d057a-8d7d-4a28-9c00-49e32e0ff1d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960342676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd ev_csr_mem_rw_with_rand_reset.1960342676 |
| Directory | /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3214758594 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 69752142 ps |
| CPU time | 0.85 seconds |
| Started | Jul 01 04:47:36 PM PDT 24 |
| Finished | Jul 01 04:47:40 PM PDT 24 |
| Peak memory | 205860 kb |
| Host | smart-7972c423-83b3-48b6-95dc-d390a7593e00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3214758594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3214758594 |
| Directory | /workspace/15.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2591101367 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 81540844 ps |
| CPU time | 0.73 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:37 PM PDT 24 |
| Peak memory | 205488 kb |
| Host | smart-1524bdbc-adf2-4c13-b96a-26a9346bd9d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2591101367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2591101367 |
| Directory | /workspace/15.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3390205029 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 95847370 ps |
| CPU time | 1.53 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:44 PM PDT 24 |
| Peak memory | 206008 kb |
| Host | smart-a726f42e-4375-4cfa-9d4a-937b8a474849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3390205029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3390205029 |
| Directory | /workspace/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.540571209 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 139450306 ps |
| CPU time | 2.03 seconds |
| Started | Jul 01 04:47:33 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 222284 kb |
| Host | smart-68825970-5dcd-4958-9011-1b878a426ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=540571209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.540571209 |
| Directory | /workspace/15.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.879651977 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 117775194 ps |
| CPU time | 2.46 seconds |
| Started | Jul 01 04:47:42 PM PDT 24 |
| Finished | Jul 01 04:47:49 PM PDT 24 |
| Peak memory | 214220 kb |
| Host | smart-3c400bd7-cda5-4fd2-86ff-71964d4d63a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879651977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde v_csr_mem_rw_with_rand_reset.879651977 |
| Directory | /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.451046544 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 55085108 ps |
| CPU time | 0.8 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:44 PM PDT 24 |
| Peak memory | 205884 kb |
| Host | smart-84796cad-00b3-49e8-bcbc-6ec06fcf5417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=451046544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.451046544 |
| Directory | /workspace/16.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.37963920 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 66235177 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 04:47:43 PM PDT 24 |
| Finished | Jul 01 04:47:49 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-9e251251-32f4-4d83-9930-15d51ddc7e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=37963920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.37963920 |
| Directory | /workspace/16.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.121089940 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 104691697 ps |
| CPU time | 1.07 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 205932 kb |
| Host | smart-b402a1ae-a40b-4041-b17e-1caadd186cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=121089940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.121089940 |
| Directory | /workspace/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3492388165 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 242074795 ps |
| CPU time | 2.99 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:47 PM PDT 24 |
| Peak memory | 221756 kb |
| Host | smart-882eb820-7ada-4a43-96c9-b84738a90f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3492388165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3492388165 |
| Directory | /workspace/16.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1961643882 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2124272561 ps |
| CPU time | 5.59 seconds |
| Started | Jul 01 04:47:42 PM PDT 24 |
| Finished | Jul 01 04:47:52 PM PDT 24 |
| Peak memory | 206140 kb |
| Host | smart-36705511-8ba8-49e9-b81c-e7695a1dfce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1961643882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1961643882 |
| Directory | /workspace/16.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2301055456 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 119837847 ps |
| CPU time | 2.74 seconds |
| Started | Jul 01 04:47:49 PM PDT 24 |
| Finished | Jul 01 04:47:58 PM PDT 24 |
| Peak memory | 214224 kb |
| Host | smart-42b969b0-4a09-44a7-8082-77e8269ccdab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301055456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.2301055456 |
| Directory | /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3591675596 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 59624207 ps |
| CPU time | 0.84 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 205888 kb |
| Host | smart-232d74ba-eff1-46aa-8cb3-d42050882d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3591675596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3591675596 |
| Directory | /workspace/17.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2704642845 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 53479048 ps |
| CPU time | 0.74 seconds |
| Started | Jul 01 04:47:43 PM PDT 24 |
| Finished | Jul 01 04:47:48 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-b03e368a-c08f-46b1-8d14-fcbb16ef1ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2704642845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2704642845 |
| Directory | /workspace/17.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3377807943 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 103061943 ps |
| CPU time | 1.22 seconds |
| Started | Jul 01 04:47:44 PM PDT 24 |
| Finished | Jul 01 04:47:50 PM PDT 24 |
| Peak memory | 205976 kb |
| Host | smart-e1497bb7-94d4-420a-8e3a-1bda0ef40b4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3377807943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3377807943 |
| Directory | /workspace/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2942270151 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 110543251 ps |
| CPU time | 1.5 seconds |
| Started | Jul 01 04:47:42 PM PDT 24 |
| Finished | Jul 01 04:47:47 PM PDT 24 |
| Peak memory | 206044 kb |
| Host | smart-df1c60a7-e9fc-49ae-9d69-e3338b627f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2942270151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2942270151 |
| Directory | /workspace/17.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1938311828 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 351426162 ps |
| CPU time | 2.9 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:47 PM PDT 24 |
| Peak memory | 206040 kb |
| Host | smart-26b8b07e-9f2e-4d7f-a2cd-0a213f473ef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1938311828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1938311828 |
| Directory | /workspace/17.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.395930115 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 144305921 ps |
| CPU time | 2.12 seconds |
| Started | Jul 01 04:47:44 PM PDT 24 |
| Finished | Jul 01 04:47:51 PM PDT 24 |
| Peak memory | 214220 kb |
| Host | smart-7ed7586f-2ae4-4926-b062-0e7721a96ec6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395930115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde v_csr_mem_rw_with_rand_reset.395930115 |
| Directory | /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1281366109 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 77455191 ps |
| CPU time | 0.89 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:45 PM PDT 24 |
| Peak memory | 205852 kb |
| Host | smart-a7d66ea4-e17f-4063-ad40-62f5fac7b406 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1281366109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1281366109 |
| Directory | /workspace/18.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3346729184 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 44332029 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:43 PM PDT 24 |
| Finished | Jul 01 04:47:49 PM PDT 24 |
| Peak memory | 205780 kb |
| Host | smart-6ffc6c61-1efc-4835-8d95-8a0290fab5b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3346729184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3346729184 |
| Directory | /workspace/18.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1137518247 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 228211383 ps |
| CPU time | 1.68 seconds |
| Started | Jul 01 04:47:42 PM PDT 24 |
| Finished | Jul 01 04:47:47 PM PDT 24 |
| Peak memory | 205960 kb |
| Host | smart-626d4292-a959-4959-b590-2b58e17c24be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1137518247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1137518247 |
| Directory | /workspace/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3802752163 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 117662486 ps |
| CPU time | 3.2 seconds |
| Started | Jul 01 04:47:42 PM PDT 24 |
| Finished | Jul 01 04:47:50 PM PDT 24 |
| Peak memory | 222396 kb |
| Host | smart-bd19159d-3c8d-4afa-9566-3a82df25c1ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3802752163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3802752163 |
| Directory | /workspace/18.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2863657345 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 93002692 ps |
| CPU time | 1.21 seconds |
| Started | Jul 01 04:47:43 PM PDT 24 |
| Finished | Jul 01 04:47:50 PM PDT 24 |
| Peak memory | 216524 kb |
| Host | smart-0c6890c4-36a0-44d4-ab6d-292d238d6335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863657345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd ev_csr_mem_rw_with_rand_reset.2863657345 |
| Directory | /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2391936781 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 42138773 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:45 PM PDT 24 |
| Peak memory | 205792 kb |
| Host | smart-e5c33111-0cd1-4422-a033-2d5b74e9321c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2391936781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2391936781 |
| Directory | /workspace/19.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.927988181 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 151985925 ps |
| CPU time | 1.8 seconds |
| Started | Jul 01 04:47:46 PM PDT 24 |
| Finished | Jul 01 04:47:54 PM PDT 24 |
| Peak memory | 205940 kb |
| Host | smart-32de4814-8674-4a0a-864c-cd2070f56d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=927988181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.927988181 |
| Directory | /workspace/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3308427602 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 198044927 ps |
| CPU time | 2.37 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:48 PM PDT 24 |
| Peak memory | 221704 kb |
| Host | smart-fddfda54-ee9b-4f84-b9e5-6264feaad816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3308427602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3308427602 |
| Directory | /workspace/19.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1219622610 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1053139590 ps |
| CPU time | 5.02 seconds |
| Started | Jul 01 04:47:42 PM PDT 24 |
| Finished | Jul 01 04:47:51 PM PDT 24 |
| Peak memory | 205940 kb |
| Host | smart-3d4d8727-8256-4860-b043-a00efc2ba958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1219622610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1219622610 |
| Directory | /workspace/19.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1345456554 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 125107096 ps |
| CPU time | 3.24 seconds |
| Started | Jul 01 04:47:14 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 206040 kb |
| Host | smart-d3d14066-a61b-465c-b3d1-6f960312d3a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1345456554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1345456554 |
| Directory | /workspace/2.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1198896430 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1468976617 ps |
| CPU time | 8.3 seconds |
| Started | Jul 01 04:47:15 PM PDT 24 |
| Finished | Jul 01 04:47:29 PM PDT 24 |
| Peak memory | 206040 kb |
| Host | smart-8921a6ea-0ddb-458a-b2da-6c93d1443806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1198896430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1198896430 |
| Directory | /workspace/2.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4156384371 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 230416704 ps |
| CPU time | 0.99 seconds |
| Started | Jul 01 04:47:14 PM PDT 24 |
| Finished | Jul 01 04:47:22 PM PDT 24 |
| Peak memory | 205880 kb |
| Host | smart-872b36b7-9893-4de3-a504-f0f20babe35b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4156384371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.4156384371 |
| Directory | /workspace/2.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1988200507 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 175430327 ps |
| CPU time | 1.85 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:25 PM PDT 24 |
| Peak memory | 214304 kb |
| Host | smart-65dca5e7-9896-4190-b77f-2da70163fe3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988200507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde v_csr_mem_rw_with_rand_reset.1988200507 |
| Directory | /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.405316409 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 54934711 ps |
| CPU time | 0.82 seconds |
| Started | Jul 01 04:47:17 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 205892 kb |
| Host | smart-ef99f14a-b838-4939-9a12-c9a18510bd33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=405316409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.405316409 |
| Directory | /workspace/2.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4231982995 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 168583759 ps |
| CPU time | 2.38 seconds |
| Started | Jul 01 04:47:14 PM PDT 24 |
| Finished | Jul 01 04:47:23 PM PDT 24 |
| Peak memory | 215308 kb |
| Host | smart-8a4543bd-7ad3-4e54-be23-c42cff739d37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4231982995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4231982995 |
| Directory | /workspace/2.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1141681861 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 171259672 ps |
| CPU time | 3.86 seconds |
| Started | Jul 01 04:47:13 PM PDT 24 |
| Finished | Jul 01 04:47:23 PM PDT 24 |
| Peak memory | 205996 kb |
| Host | smart-50318cbe-9ec4-4fa5-818e-b5560cb90f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1141681861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1141681861 |
| Directory | /workspace/2.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.997257361 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 91528005 ps |
| CPU time | 1.08 seconds |
| Started | Jul 01 04:47:17 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 205980 kb |
| Host | smart-ac3c3fdc-045e-440b-ade3-f5d9a56b9a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=997257361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.997257361 |
| Directory | /workspace/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2442448627 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 120528049 ps |
| CPU time | 2.89 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:25 PM PDT 24 |
| Peak memory | 214184 kb |
| Host | smart-a02d5532-3d8c-4584-8793-d53ba559a09f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2442448627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2442448627 |
| Directory | /workspace/2.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.685383911 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 365561353 ps |
| CPU time | 2.78 seconds |
| Started | Jul 01 04:47:15 PM PDT 24 |
| Finished | Jul 01 04:47:24 PM PDT 24 |
| Peak memory | 206008 kb |
| Host | smart-92450aec-7fce-4acb-8bd0-7ff30e0c336f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=685383911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.685383911 |
| Directory | /workspace/2.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1874417855 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 97239262 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 04:47:49 PM PDT 24 |
| Finished | Jul 01 04:47:56 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-459108fe-65a0-4a72-9b05-3750c9e54d9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1874417855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1874417855 |
| Directory | /workspace/20.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.919431574 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 48542451 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:45 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-21ef850b-3686-470c-988c-281e772523c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=919431574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.919431574 |
| Directory | /workspace/22.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.930839586 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 58853907 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:39 PM PDT 24 |
| Finished | Jul 01 04:47:42 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-14721830-62ec-46c5-9543-8156c64e491b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=930839586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.930839586 |
| Directory | /workspace/23.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.484103856 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 43065180 ps |
| CPU time | 0.67 seconds |
| Started | Jul 01 04:47:45 PM PDT 24 |
| Finished | Jul 01 04:47:51 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-904ce5d1-ebcf-4952-a4df-a712e9eadfce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=484103856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.484103856 |
| Directory | /workspace/24.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2885065403 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 44638361 ps |
| CPU time | 0.73 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:43 PM PDT 24 |
| Peak memory | 205788 kb |
| Host | smart-34109210-f18b-4ed0-a40e-983571c7601d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2885065403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2885065403 |
| Directory | /workspace/25.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2677124970 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 54879071 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 205800 kb |
| Host | smart-d065e304-c919-4695-aac4-2c0cafc801d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2677124970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2677124970 |
| Directory | /workspace/26.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4134336054 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 37838190 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 205816 kb |
| Host | smart-47cb712a-f5f4-4e1a-a138-64f31781fd55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4134336054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4134336054 |
| Directory | /workspace/27.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1973147021 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 61254695 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 04:47:50 PM PDT 24 |
| Finished | Jul 01 04:47:56 PM PDT 24 |
| Peak memory | 205764 kb |
| Host | smart-de00f5de-136f-4862-9877-3e5aa1c4521c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1973147021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1973147021 |
| Directory | /workspace/28.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3915736441 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 73617154 ps |
| CPU time | 0.79 seconds |
| Started | Jul 01 04:47:42 PM PDT 24 |
| Finished | Jul 01 04:47:48 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-0ddb19f0-1967-48d5-bc76-84635700223e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3915736441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3915736441 |
| Directory | /workspace/29.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3484930238 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 79153015 ps |
| CPU time | 2.15 seconds |
| Started | Jul 01 04:47:20 PM PDT 24 |
| Finished | Jul 01 04:47:29 PM PDT 24 |
| Peak memory | 206104 kb |
| Host | smart-7e89086e-2d15-4471-9df4-4d55cc0958ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3484930238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3484930238 |
| Directory | /workspace/3.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3577159859 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 173576191 ps |
| CPU time | 3.78 seconds |
| Started | Jul 01 04:47:20 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 206008 kb |
| Host | smart-18230251-d605-4113-91cb-3075cc643a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3577159859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3577159859 |
| Directory | /workspace/3.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2206762718 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 93593315 ps |
| CPU time | 1.63 seconds |
| Started | Jul 01 04:47:30 PM PDT 24 |
| Finished | Jul 01 04:47:33 PM PDT 24 |
| Peak memory | 213684 kb |
| Host | smart-07a28cf4-fcca-4254-876d-8f768e63cd49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206762718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde v_csr_mem_rw_with_rand_reset.2206762718 |
| Directory | /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2058315224 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 59421197 ps |
| CPU time | 0.8 seconds |
| Started | Jul 01 04:47:20 PM PDT 24 |
| Finished | Jul 01 04:47:27 PM PDT 24 |
| Peak memory | 205860 kb |
| Host | smart-7b7c4b13-bb0f-4459-ac24-1432b1297324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2058315224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2058315224 |
| Directory | /workspace/3.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4000790293 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 85685155 ps |
| CPU time | 0.74 seconds |
| Started | Jul 01 04:47:22 PM PDT 24 |
| Finished | Jul 01 04:47:28 PM PDT 24 |
| Peak memory | 205848 kb |
| Host | smart-945c1247-2d04-4c70-994c-2fbcfbc59b92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4000790293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.4000790293 |
| Directory | /workspace/3.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2401364189 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 78757727 ps |
| CPU time | 2.34 seconds |
| Started | Jul 01 04:47:20 PM PDT 24 |
| Finished | Jul 01 04:47:29 PM PDT 24 |
| Peak memory | 214220 kb |
| Host | smart-fad7645b-c95d-479a-9ed8-29298f37be03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2401364189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2401364189 |
| Directory | /workspace/3.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2957203965 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 106795569 ps |
| CPU time | 2.35 seconds |
| Started | Jul 01 04:47:22 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 205992 kb |
| Host | smart-999cf9e3-b13f-476f-8a4e-914792dd8420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2957203965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2957203965 |
| Directory | /workspace/3.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.793044855 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 156614628 ps |
| CPU time | 1.52 seconds |
| Started | Jul 01 04:47:24 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 206036 kb |
| Host | smart-dd7ae111-22cd-4848-99b4-891ddbfcdd85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=793044855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.793044855 |
| Directory | /workspace/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1342451737 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 107345466 ps |
| CPU time | 1.97 seconds |
| Started | Jul 01 04:47:16 PM PDT 24 |
| Finished | Jul 01 04:47:25 PM PDT 24 |
| Peak memory | 222344 kb |
| Host | smart-4fc508c5-6fd1-4064-9897-856cbff4d2b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1342451737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1342451737 |
| Directory | /workspace/3.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2328336946 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 526337308 ps |
| CPU time | 4.28 seconds |
| Started | Jul 01 04:47:30 PM PDT 24 |
| Finished | Jul 01 04:47:36 PM PDT 24 |
| Peak memory | 205524 kb |
| Host | smart-d625dcee-f18d-4f7b-b796-ddbe9b544e2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2328336946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2328336946 |
| Directory | /workspace/3.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1072065081 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 94973799 ps |
| CPU time | 0.74 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:46 PM PDT 24 |
| Peak memory | 205876 kb |
| Host | smart-bac6d29e-710a-4b7d-8480-6a51dc25ae26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1072065081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1072065081 |
| Directory | /workspace/30.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3902600680 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 53504019 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 04:47:46 PM PDT 24 |
| Finished | Jul 01 04:47:53 PM PDT 24 |
| Peak memory | 205804 kb |
| Host | smart-098c6639-eb91-48fb-a79c-5edfa1a6ee31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3902600680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3902600680 |
| Directory | /workspace/31.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2842979478 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 36153099 ps |
| CPU time | 0.65 seconds |
| Started | Jul 01 04:47:43 PM PDT 24 |
| Finished | Jul 01 04:47:49 PM PDT 24 |
| Peak memory | 205792 kb |
| Host | smart-e7f39985-c444-47b0-8751-301bc719f540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2842979478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2842979478 |
| Directory | /workspace/32.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.107843544 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 45767034 ps |
| CPU time | 0.75 seconds |
| Started | Jul 01 04:47:49 PM PDT 24 |
| Finished | Jul 01 04:47:56 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-f4512ed5-b80d-4835-937f-acedd3973f22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=107843544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.107843544 |
| Directory | /workspace/33.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3945101846 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 36137110 ps |
| CPU time | 0.71 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:45 PM PDT 24 |
| Peak memory | 205924 kb |
| Host | smart-5ca784b0-d5b5-4bd8-a841-4314e6be4a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3945101846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3945101846 |
| Directory | /workspace/34.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1495834981 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 56870820 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 04:47:42 PM PDT 24 |
| Finished | Jul 01 04:47:47 PM PDT 24 |
| Peak memory | 205900 kb |
| Host | smart-aedd8557-18b8-433c-bda4-00a8a95b1b53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1495834981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1495834981 |
| Directory | /workspace/35.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2478242856 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 42999447 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 04:47:50 PM PDT 24 |
| Finished | Jul 01 04:47:56 PM PDT 24 |
| Peak memory | 205764 kb |
| Host | smart-3e2a71ef-d6ed-406e-9966-5d0c85f4a10c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2478242856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2478242856 |
| Directory | /workspace/36.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1856031403 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 46312457 ps |
| CPU time | 0.71 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:44 PM PDT 24 |
| Peak memory | 205768 kb |
| Host | smart-850370a1-5f73-4176-98eb-61b82dcc913d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1856031403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1856031403 |
| Directory | /workspace/37.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4066097486 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 68656218 ps |
| CPU time | 0.75 seconds |
| Started | Jul 01 04:47:46 PM PDT 24 |
| Finished | Jul 01 04:47:53 PM PDT 24 |
| Peak memory | 205788 kb |
| Host | smart-f7fb5657-4af2-4695-884b-d943d8aa2975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4066097486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4066097486 |
| Directory | /workspace/38.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1782110822 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 376153813 ps |
| CPU time | 3.52 seconds |
| Started | Jul 01 04:47:19 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 205996 kb |
| Host | smart-ff4e5374-8f44-4084-9662-8fe0fa0331ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1782110822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1782110822 |
| Directory | /workspace/4.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3408968198 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 615090644 ps |
| CPU time | 4.38 seconds |
| Started | Jul 01 04:47:26 PM PDT 24 |
| Finished | Jul 01 04:47:35 PM PDT 24 |
| Peak memory | 206108 kb |
| Host | smart-dec2ecdb-7b63-4b02-829d-152275b94f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3408968198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3408968198 |
| Directory | /workspace/4.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2021724850 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 178022356 ps |
| CPU time | 1.4 seconds |
| Started | Jul 01 04:47:21 PM PDT 24 |
| Finished | Jul 01 04:47:28 PM PDT 24 |
| Peak memory | 214216 kb |
| Host | smart-7e47659b-9c7d-44c9-afea-3a71c4ac0d3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021724850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde v_csr_mem_rw_with_rand_reset.2021724850 |
| Directory | /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.460718650 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 73802533 ps |
| CPU time | 1.05 seconds |
| Started | Jul 01 04:47:23 PM PDT 24 |
| Finished | Jul 01 04:47:29 PM PDT 24 |
| Peak memory | 206172 kb |
| Host | smart-b338014c-9ac7-498b-8038-06c33a1f5d7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=460718650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.460718650 |
| Directory | /workspace/4.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4282696840 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 42445481 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 04:47:23 PM PDT 24 |
| Finished | Jul 01 04:47:28 PM PDT 24 |
| Peak memory | 205796 kb |
| Host | smart-d78b4918-8b2b-43b9-9993-b1a0cf87e3d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4282696840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.4282696840 |
| Directory | /workspace/4.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2062588948 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 164694169 ps |
| CPU time | 2.29 seconds |
| Started | Jul 01 04:47:22 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 215352 kb |
| Host | smart-d4ddc96e-ee13-4d09-b054-84f5c5e613a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2062588948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2062588948 |
| Directory | /workspace/4.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1056982097 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 373304768 ps |
| CPU time | 2.65 seconds |
| Started | Jul 01 04:47:22 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 205952 kb |
| Host | smart-48c89162-0e9e-41b2-9458-98b19d78e3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1056982097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1056982097 |
| Directory | /workspace/4.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.522268753 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 193655030 ps |
| CPU time | 1.09 seconds |
| Started | Jul 01 04:47:22 PM PDT 24 |
| Finished | Jul 01 04:47:28 PM PDT 24 |
| Peak memory | 205968 kb |
| Host | smart-fc12e4ce-2241-4892-9dbf-17673bfe0af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=522268753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.522268753 |
| Directory | /workspace/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.625797715 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 168078463 ps |
| CPU time | 2.04 seconds |
| Started | Jul 01 04:47:24 PM PDT 24 |
| Finished | Jul 01 04:47:31 PM PDT 24 |
| Peak memory | 206060 kb |
| Host | smart-b3926c93-f8f7-4ade-a81f-8004966614ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=625797715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.625797715 |
| Directory | /workspace/4.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2865291115 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 368366333 ps |
| CPU time | 2.96 seconds |
| Started | Jul 01 04:47:23 PM PDT 24 |
| Finished | Jul 01 04:47:31 PM PDT 24 |
| Peak memory | 205980 kb |
| Host | smart-a3093333-5364-42d6-80df-f3d16ec4f90a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2865291115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2865291115 |
| Directory | /workspace/4.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3323444269 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 46483491 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 04:47:40 PM PDT 24 |
| Finished | Jul 01 04:47:43 PM PDT 24 |
| Peak memory | 205796 kb |
| Host | smart-47efc8a3-cb18-4278-b3e7-9ad8349899d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3323444269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3323444269 |
| Directory | /workspace/40.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2542611201 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 55620450 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:43 PM PDT 24 |
| Finished | Jul 01 04:47:47 PM PDT 24 |
| Peak memory | 205792 kb |
| Host | smart-2371b4f7-5bfd-46c8-b7f2-6c46163e55d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2542611201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2542611201 |
| Directory | /workspace/41.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.707388071 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 57208822 ps |
| CPU time | 0.73 seconds |
| Started | Jul 01 04:47:46 PM PDT 24 |
| Finished | Jul 01 04:47:53 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-05603760-0d71-483d-8027-d0b5d84f8143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=707388071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.707388071 |
| Directory | /workspace/42.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.566115240 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 36555572 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 04:47:43 PM PDT 24 |
| Finished | Jul 01 04:47:49 PM PDT 24 |
| Peak memory | 205788 kb |
| Host | smart-fe63fb92-52df-4b0c-8229-e7f304f376cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=566115240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.566115240 |
| Directory | /workspace/43.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2602836491 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 38714240 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:49 PM PDT 24 |
| Finished | Jul 01 04:47:55 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-9226f16f-08c2-486f-974a-23b6ad336bb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2602836491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2602836491 |
| Directory | /workspace/44.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.856687590 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 51139847 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:45 PM PDT 24 |
| Finished | Jul 01 04:47:51 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-bced396f-4d6d-4007-9477-e8a85b1fbddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=856687590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.856687590 |
| Directory | /workspace/45.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2571845893 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 39382450 ps |
| CPU time | 0.67 seconds |
| Started | Jul 01 04:47:41 PM PDT 24 |
| Finished | Jul 01 04:47:45 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-c005d04f-9513-422b-9813-1d42460a14bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2571845893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2571845893 |
| Directory | /workspace/46.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1071092045 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 36070485 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 04:47:39 PM PDT 24 |
| Finished | Jul 01 04:47:43 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-c9ea7f91-1341-4f60-b0ea-045d5fff7dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1071092045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1071092045 |
| Directory | /workspace/47.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1585572168 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 41218748 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 04:47:51 PM PDT 24 |
| Finished | Jul 01 04:47:57 PM PDT 24 |
| Peak memory | 205792 kb |
| Host | smart-68cee939-b799-40d2-bbe5-4c518ecac447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1585572168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1585572168 |
| Directory | /workspace/49.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3787294310 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 118597804 ps |
| CPU time | 1.3 seconds |
| Started | Jul 01 04:47:30 PM PDT 24 |
| Finished | Jul 01 04:47:33 PM PDT 24 |
| Peak memory | 214168 kb |
| Host | smart-ebff9c2a-3219-452b-b736-1d7a5d2061cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787294310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde v_csr_mem_rw_with_rand_reset.3787294310 |
| Directory | /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2449293462 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 72963891 ps |
| CPU time | 0.83 seconds |
| Started | Jul 01 04:47:25 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 205964 kb |
| Host | smart-f48f2a48-5d81-4423-bb68-6fc5335a0475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2449293462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2449293462 |
| Directory | /workspace/5.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.204453522 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 36304303 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 04:47:24 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-0325fb36-c110-4401-a848-65a88a1d2eb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=204453522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.204453522 |
| Directory | /workspace/5.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2589197538 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 158656922 ps |
| CPU time | 1.77 seconds |
| Started | Jul 01 04:47:22 PM PDT 24 |
| Finished | Jul 01 04:47:29 PM PDT 24 |
| Peak memory | 206064 kb |
| Host | smart-41b79a18-19c6-4a02-97c8-c35215c4d42a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2589197538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2589197538 |
| Directory | /workspace/5.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1107520666 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 124860783 ps |
| CPU time | 1.78 seconds |
| Started | Jul 01 04:47:22 PM PDT 24 |
| Finished | Jul 01 04:47:29 PM PDT 24 |
| Peak memory | 221984 kb |
| Host | smart-8d426629-e980-40b5-ab01-fc8adcc99fb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1107520666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1107520666 |
| Directory | /workspace/5.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1335498127 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1553480800 ps |
| CPU time | 5.02 seconds |
| Started | Jul 01 04:47:21 PM PDT 24 |
| Finished | Jul 01 04:47:32 PM PDT 24 |
| Peak memory | 205988 kb |
| Host | smart-f38e1223-4290-4065-8285-3654af95efcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1335498127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1335498127 |
| Directory | /workspace/5.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2630612746 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 96117084 ps |
| CPU time | 1.38 seconds |
| Started | Jul 01 04:47:23 PM PDT 24 |
| Finished | Jul 01 04:47:29 PM PDT 24 |
| Peak memory | 214228 kb |
| Host | smart-8f49a690-3f02-4987-a66b-b3a3f01c6df0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630612746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde v_csr_mem_rw_with_rand_reset.2630612746 |
| Directory | /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3771938602 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 83165446 ps |
| CPU time | 0.85 seconds |
| Started | Jul 01 04:47:24 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 205832 kb |
| Host | smart-18b79e7a-7d8c-476d-ad26-7df9c2b6b945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3771938602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3771938602 |
| Directory | /workspace/6.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3676412968 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 75628132 ps |
| CPU time | 0.74 seconds |
| Started | Jul 01 04:47:22 PM PDT 24 |
| Finished | Jul 01 04:47:28 PM PDT 24 |
| Peak memory | 205820 kb |
| Host | smart-28fca92e-e1b8-452c-8a6b-965f7540459c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3676412968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3676412968 |
| Directory | /workspace/6.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2813400553 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 175138121 ps |
| CPU time | 1.81 seconds |
| Started | Jul 01 04:47:21 PM PDT 24 |
| Finished | Jul 01 04:47:29 PM PDT 24 |
| Peak memory | 206096 kb |
| Host | smart-eaeccdfc-1716-4066-9b3a-9fb9ec526e42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2813400553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2813400553 |
| Directory | /workspace/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.736352725 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 268818343 ps |
| CPU time | 3.21 seconds |
| Started | Jul 01 04:47:25 PM PDT 24 |
| Finished | Jul 01 04:47:33 PM PDT 24 |
| Peak memory | 221776 kb |
| Host | smart-051c3519-1760-4995-8502-d626daca708a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=736352725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.736352725 |
| Directory | /workspace/6.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2342374921 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 107961309 ps |
| CPU time | 2.88 seconds |
| Started | Jul 01 04:47:24 PM PDT 24 |
| Finished | Jul 01 04:47:31 PM PDT 24 |
| Peak memory | 214220 kb |
| Host | smart-56491b67-11df-49db-954e-0c3384fa21df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342374921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde v_csr_mem_rw_with_rand_reset.2342374921 |
| Directory | /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.369838891 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 96353802 ps |
| CPU time | 0.85 seconds |
| Started | Jul 01 04:47:30 PM PDT 24 |
| Finished | Jul 01 04:47:33 PM PDT 24 |
| Peak memory | 205836 kb |
| Host | smart-9cfc1565-cc93-401a-bdc5-40eb9bb3b49b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=369838891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.369838891 |
| Directory | /workspace/7.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1061470461 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 71511339 ps |
| CPU time | 0.74 seconds |
| Started | Jul 01 04:47:25 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 205800 kb |
| Host | smart-6292e08e-e921-4a3d-a944-2e9789c8b572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1061470461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1061470461 |
| Directory | /workspace/7.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1547444424 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 267752998 ps |
| CPU time | 1.87 seconds |
| Started | Jul 01 04:47:28 PM PDT 24 |
| Finished | Jul 01 04:47:33 PM PDT 24 |
| Peak memory | 206000 kb |
| Host | smart-02e109f8-f303-4652-8bb5-e899c2426c7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1547444424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1547444424 |
| Directory | /workspace/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2901477946 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 238113295 ps |
| CPU time | 2.34 seconds |
| Started | Jul 01 04:47:30 PM PDT 24 |
| Finished | Jul 01 04:47:34 PM PDT 24 |
| Peak memory | 221244 kb |
| Host | smart-ea368231-fe68-4de2-b725-77ca29e21aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2901477946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2901477946 |
| Directory | /workspace/7.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2566725020 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 563833196 ps |
| CPU time | 4.23 seconds |
| Started | Jul 01 04:47:23 PM PDT 24 |
| Finished | Jul 01 04:47:32 PM PDT 24 |
| Peak memory | 205968 kb |
| Host | smart-1950400b-3175-4d8d-9e83-cd513cfb31a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2566725020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2566725020 |
| Directory | /workspace/7.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.753725239 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 101289002 ps |
| CPU time | 1.6 seconds |
| Started | Jul 01 04:47:24 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 214236 kb |
| Host | smart-8ea906da-bd2a-47ff-82fb-c1deee4f5565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753725239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev _csr_mem_rw_with_rand_reset.753725239 |
| Directory | /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1469244694 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 122088081 ps |
| CPU time | 1.02 seconds |
| Started | Jul 01 04:47:28 PM PDT 24 |
| Finished | Jul 01 04:47:32 PM PDT 24 |
| Peak memory | 206016 kb |
| Host | smart-4f1ad667-a055-4b5e-8e39-d35f3d84af9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1469244694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1469244694 |
| Directory | /workspace/8.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1315162242 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 43782380 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 04:47:20 PM PDT 24 |
| Finished | Jul 01 04:47:27 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-b5ba5593-e68d-45ee-8841-a55f17024fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1315162242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1315162242 |
| Directory | /workspace/8.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1545270903 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 161287147 ps |
| CPU time | 1.58 seconds |
| Started | Jul 01 04:47:27 PM PDT 24 |
| Finished | Jul 01 04:47:33 PM PDT 24 |
| Peak memory | 206092 kb |
| Host | smart-d8aaf219-d84d-40da-a18d-4b55786cc63b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1545270903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1545270903 |
| Directory | /workspace/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.238954338 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 209023097 ps |
| CPU time | 2.29 seconds |
| Started | Jul 01 04:47:23 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 221932 kb |
| Host | smart-76dbdf43-0182-46f0-9157-c4cb19fc2b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=238954338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.238954338 |
| Directory | /workspace/8.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.903785947 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 742671060 ps |
| CPU time | 2.98 seconds |
| Started | Jul 01 04:47:21 PM PDT 24 |
| Finished | Jul 01 04:47:30 PM PDT 24 |
| Peak memory | 206052 kb |
| Host | smart-cbb9e7c3-2e89-473f-8084-80d32881faf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=903785947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.903785947 |
| Directory | /workspace/8.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3897522470 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 131709946 ps |
| CPU time | 1.75 seconds |
| Started | Jul 01 04:47:32 PM PDT 24 |
| Finished | Jul 01 04:47:36 PM PDT 24 |
| Peak memory | 214164 kb |
| Host | smart-0cf971a1-736d-43f1-9976-2e2f20f44c31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897522470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde v_csr_mem_rw_with_rand_reset.3897522470 |
| Directory | /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1997481701 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 58654337 ps |
| CPU time | 0.96 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-7014b42a-a013-4a4b-a361-fd65aeb15c9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1997481701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1997481701 |
| Directory | /workspace/9.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.731841868 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 49601798 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 04:47:34 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 205440 kb |
| Host | smart-dfdd182a-b7f6-4ffd-aedb-27abb6fe1689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=731841868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.731841868 |
| Directory | /workspace/9.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2313533167 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 142829516 ps |
| CPU time | 1.66 seconds |
| Started | Jul 01 04:47:37 PM PDT 24 |
| Finished | Jul 01 04:47:41 PM PDT 24 |
| Peak memory | 206000 kb |
| Host | smart-6d640cda-b6b7-400d-b2c3-971025c791c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2313533167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2313533167 |
| Directory | /workspace/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4013660212 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 150288839 ps |
| CPU time | 1.81 seconds |
| Started | Jul 01 04:47:31 PM PDT 24 |
| Finished | Jul 01 04:47:35 PM PDT 24 |
| Peak memory | 206124 kb |
| Host | smart-546f464e-3d36-455a-b508-fd5b9dcfcb27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4013660212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4013660212 |
| Directory | /workspace/9.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.11898872 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 423621400 ps |
| CPU time | 3.18 seconds |
| Started | Jul 01 04:47:32 PM PDT 24 |
| Finished | Jul 01 04:47:38 PM PDT 24 |
| Peak memory | 206028 kb |
| Host | smart-d6be6e64-7d53-42fb-9002-b25ab77d7aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=11898872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.11898872 |
| Directory | /workspace/9.usbdev_tl_intg_err/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |