Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T1	7		T3	7		T16	4
all_values[1]	281	1		T1	7		T3	7		T16	4
all_values[2]	281	1		T1	7		T3	7		T16	4
all_values[3]	281	1		T1	7		T3	7		T16	4
all_values[4]	281	1		T1	7		T3	7		T16	4
all_values[5]	281	1		T1	7		T3	7		T16	4
all_values[6]	281	1		T1	7		T3	7		T16	4
all_values[7]	281	1		T1	7		T3	7		T16	4
all_values[8]	281	1		T1	7		T3	7		T16	4
all_values[9]	281	1		T1	7		T3	7		T16	4
all_values[10]	281	1		T1	7		T3	7		T16	4
all_values[11]	281	1		T1	7		T3	7		T16	4
all_values[12]	281	1		T1	7		T3	7		T16	4
all_values[13]	281	1		T1	7		T3	7		T16	4
all_values[14]	281	1		T1	7		T3	7		T16	4
all_values[15]	281	1		T1	7		T3	7		T16	4
all_values[16]	281	1		T1	7		T3	7		T16	4
all_values[17]	281	1		T1	7		T3	7		T16	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2812	1		T1	64		T3	76		T16	40
auto[1]	2246	1		T1	62		T3	50		T16	32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	888	1		T1	19		T3	21		T16	15
auto[1]	4170	1		T1	107		T3	105		T16	57

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2990	1		T1	68		T3	74		T16	44
auto[1]	2068	1		T1	58		T3	52		T16	28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1		T15	1		T38	3		T55	2
all_values[0]	auto[0]	auto[0]	auto[1]	67	1		T1	3		T3	3		T14	2
all_values[0]	auto[0]	auto[1]	auto[0]	16	1		T14	1		T38	2		T55	2
all_values[0]	auto[0]	auto[1]	auto[1]	50	1		T1	1		T16	3		T38	1
all_values[0]	auto[1]	auto[0]	auto[1]	58	1		T1	2		T3	3		T14	3
all_values[0]	auto[1]	auto[1]	auto[1]	57	1		T1	1		T3	1		T16	1
all_values[1]	auto[0]	auto[0]	auto[0]	32	1		T14	1		T38	1		T57	1
all_values[1]	auto[0]	auto[0]	auto[1]	66	1		T1	1		T3	5		T16	1
all_values[1]	auto[0]	auto[1]	auto[0]	23	1		T1	1		T14	1		T38	1
all_values[1]	auto[0]	auto[1]	auto[1]	56	1		T1	2		T16	1		T14	2
all_values[1]	auto[1]	auto[0]	auto[1]	68	1		T1	1		T3	2		T16	2
all_values[1]	auto[1]	auto[1]	auto[1]	36	1		T1	2		T14	1		T15	1
all_values[2]	auto[0]	auto[0]	auto[0]	34	1		T1	1		T3	2		T15	3
all_values[2]	auto[0]	auto[0]	auto[1]	43	1		T14	1		T59	1		T60	5
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T3	2		T15	1		T38	1
all_values[2]	auto[0]	auto[1]	auto[1]	65	1		T1	4		T3	1		T16	1
all_values[2]	auto[1]	auto[0]	auto[1]	63	1		T1	1		T16	3		T14	6
all_values[2]	auto[1]	auto[1]	auto[1]	60	1		T1	1		T3	2		T38	2
all_values[3]	auto[0]	auto[0]	auto[0]	23	1		T1	1		T14	2		T38	2
all_values[3]	auto[0]	auto[0]	auto[1]	58	1		T3	2		T16	1		T15	2
all_values[3]	auto[0]	auto[1]	auto[0]	27	1		T1	3		T14	1		T57	3
all_values[3]	auto[0]	auto[1]	auto[1]	52	1		T1	1		T3	1		T16	2
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T3	4		T14	1		T15	2
all_values[3]	auto[1]	auto[1]	auto[1]	61	1		T1	2		T16	1		T14	1
all_values[4]	auto[0]	auto[0]	auto[0]	35	1		T1	1		T3	1		T15	1
all_values[4]	auto[0]	auto[0]	auto[1]	61	1		T1	1		T3	2		T16	2
all_values[4]	auto[0]	auto[1]	auto[0]	28	1		T1	2		T14	3		T38	1
all_values[4]	auto[0]	auto[1]	auto[1]	52	1		T3	1		T14	1		T15	2
all_values[4]	auto[1]	auto[0]	auto[1]	59	1		T1	3		T3	1		T16	2
all_values[4]	auto[1]	auto[1]	auto[1]	46	1		T3	2		T14	1		T15	1
all_values[5]	auto[0]	auto[0]	auto[0]	24	1		T3	1		T15	1		T59	1
all_values[5]	auto[0]	auto[0]	auto[1]	46	1		T1	2		T16	1		T14	1
all_values[5]	auto[0]	auto[1]	auto[0]	16	1		T55	1		T60	3		T63	4
all_values[5]	auto[0]	auto[1]	auto[1]	68	1		T3	1		T14	3		T15	1
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T1	1		T3	1		T16	3
all_values[5]	auto[1]	auto[1]	auto[1]	63	1		T1	4		T3	4		T14	2
all_values[6]	auto[0]	auto[0]	auto[0]	24	1		T55	1		T59	1		T56	1
all_values[6]	auto[0]	auto[0]	auto[1]	54	1		T3	3		T16	2		T14	1
all_values[6]	auto[0]	auto[1]	auto[0]	11	1		T14	1		T64	3		T65	2
all_values[6]	auto[0]	auto[1]	auto[1]	67	1		T1	3		T3	1		T14	3
all_values[6]	auto[1]	auto[0]	auto[1]	71	1		T3	3		T16	2		T14	1
all_values[6]	auto[1]	auto[1]	auto[1]	54	1		T1	4		T14	1		T38	2
all_values[7]	auto[0]	auto[0]	auto[0]	39	1		T3	1		T16	2		T38	1
all_values[7]	auto[0]	auto[0]	auto[1]	52	1		T1	2		T3	2		T14	1
all_values[7]	auto[0]	auto[1]	auto[0]	18	1		T14	2		T38	1		T66	1
all_values[7]	auto[0]	auto[1]	auto[1]	53	1		T1	1		T3	2		T16	1
all_values[7]	auto[1]	auto[0]	auto[1]	66	1		T1	4		T16	1		T14	1
all_values[7]	auto[1]	auto[1]	auto[1]	53	1		T3	2		T14	2		T38	2
all_values[8]	auto[0]	auto[0]	auto[0]	25	1		T3	1		T14	1		T60	1
all_values[8]	auto[0]	auto[0]	auto[1]	63	1		T1	1		T3	2		T16	1
all_values[8]	auto[0]	auto[1]	auto[0]	13	1		T1	1		T14	1		T60	1
all_values[8]	auto[0]	auto[1]	auto[1]	56	1		T3	1		T15	3		T38	3
all_values[8]	auto[1]	auto[0]	auto[1]	76	1		T1	4		T3	1		T16	1
all_values[8]	auto[1]	auto[1]	auto[1]	48	1		T1	1		T3	2		T16	2
all_values[9]	auto[0]	auto[0]	auto[0]	34	1		T3	1		T15	1		T38	2
all_values[9]	auto[0]	auto[0]	auto[1]	75	1		T1	2		T3	1		T14	2
all_values[9]	auto[0]	auto[1]	auto[0]	21	1		T1	1		T16	4		T38	1
all_values[9]	auto[0]	auto[1]	auto[1]	49	1		T3	2		T14	2		T15	1
all_values[9]	auto[1]	auto[0]	auto[1]	60	1		T1	3		T3	1		T15	1
all_values[9]	auto[1]	auto[1]	auto[1]	42	1		T1	1		T3	2		T14	3
all_values[10]	auto[0]	auto[0]	auto[0]	26	1		T15	4		T38	1		T59	1
all_values[10]	auto[0]	auto[0]	auto[1]	63	1		T1	2		T3	3		T16	2
all_values[10]	auto[0]	auto[1]	auto[0]	10	1		T55	2		T60	2		T66	2
all_values[10]	auto[0]	auto[1]	auto[1]	65	1		T1	1		T14	2		T38	1
all_values[10]	auto[1]	auto[0]	auto[1]	74	1		T1	3		T3	4		T16	2
all_values[10]	auto[1]	auto[1]	auto[1]	43	1		T1	1		T14	3		T38	1
all_values[11]	auto[0]	auto[0]	auto[0]	34	1		T16	2		T14	1		T38	1
all_values[11]	auto[0]	auto[0]	auto[1]	64	1		T16	1		T14	2		T38	2
all_values[11]	auto[0]	auto[1]	auto[0]	19	1		T14	1		T55	4		T61	1
all_values[11]	auto[0]	auto[1]	auto[1]	54	1		T1	3		T3	4		T15	1
all_values[11]	auto[1]	auto[0]	auto[1]	63	1		T3	3		T16	1		T14	3
all_values[11]	auto[1]	auto[1]	auto[1]	47	1		T1	4		T15	2		T60	1
all_values[12]	auto[0]	auto[0]	auto[0]	34	1		T3	1		T16	3		T59	1
all_values[12]	auto[0]	auto[0]	auto[1]	73	1		T1	5		T3	2		T14	1
all_values[12]	auto[0]	auto[1]	auto[0]	13	1		T16	1		T14	1		T55	1
all_values[12]	auto[0]	auto[1]	auto[1]	42	1		T1	1		T3	2		T38	4
all_values[12]	auto[1]	auto[0]	auto[1]	69	1		T3	1		T15	2		T38	2
all_values[12]	auto[1]	auto[1]	auto[1]	50	1		T1	1		T3	1		T14	5
all_values[13]	auto[0]	auto[0]	auto[0]	32	1		T1	1		T3	1		T14	1
all_values[13]	auto[0]	auto[0]	auto[1]	68	1		T1	4		T3	2		T16	1
all_values[13]	auto[0]	auto[1]	auto[0]	18	1		T38	1		T60	2		T66	2
all_values[13]	auto[0]	auto[1]	auto[1]	44	1		T16	1		T15	2		T38	1
all_values[13]	auto[1]	auto[0]	auto[1]	62	1		T1	2		T3	1		T16	1
all_values[13]	auto[1]	auto[1]	auto[1]	57	1		T3	3		T16	1		T14	2
all_values[14]	auto[0]	auto[0]	auto[0]	37	1		T1	1		T3	1		T15	1
all_values[14]	auto[0]	auto[0]	auto[1]	66	1		T1	1		T3	1		T14	3
all_values[14]	auto[0]	auto[1]	auto[0]	17	1		T1	2		T16	1		T38	1
all_values[14]	auto[0]	auto[1]	auto[1]	53	1		T1	1		T3	2		T16	2
all_values[14]	auto[1]	auto[0]	auto[1]	64	1		T1	1		T3	2		T14	1
all_values[14]	auto[1]	auto[1]	auto[1]	44	1		T1	1		T3	1		T16	1
all_values[15]	auto[0]	auto[0]	auto[0]	35	1		T3	2		T14	1		T59	1
all_values[15]	auto[0]	auto[0]	auto[1]	58	1		T1	1		T3	1		T16	2
all_values[15]	auto[0]	auto[1]	auto[0]	18	1		T16	1		T59	1		T64	1
all_values[15]	auto[0]	auto[1]	auto[1]	58	1		T1	2		T3	2		T14	2
all_values[15]	auto[1]	auto[0]	auto[1]	62	1		T1	3		T3	2		T16	1
all_values[15]	auto[1]	auto[1]	auto[1]	50	1		T1	1		T14	1		T38	3
all_values[16]	auto[0]	auto[0]	auto[0]	36	1		T3	2		T15	4		T38	1
all_values[16]	auto[0]	auto[0]	auto[1]	71	1		T1	2		T14	4		T38	1
all_values[16]	auto[0]	auto[1]	auto[0]	18	1		T3	3		T16	1		T63	2
all_values[16]	auto[0]	auto[1]	auto[1]	56	1		T1	1		T3	1		T16	2
all_values[16]	auto[1]	auto[0]	auto[1]	50	1		T1	1		T14	2		T38	1
all_values[16]	auto[1]	auto[1]	auto[1]	50	1		T1	3		T3	1		T16	1
all_values[17]	auto[0]	auto[0]	auto[0]	24	1		T1	1		T3	1		T15	1
all_values[17]	auto[0]	auto[0]	auto[1]	53	1		T1	1		T3	1		T14	1
all_values[17]	auto[0]	auto[1]	auto[0]	25	1		T1	3		T3	1		T14	1
all_values[17]	auto[0]	auto[1]	auto[1]	61	1		T3	2		T16	2		T14	1
all_values[17]	auto[1]	auto[0]	auto[1]	61	1		T1	1		T3	2		T14	3
all_values[17]	auto[1]	auto[1]	auto[1]	57	1		T1	1		T16	2		T14	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal