Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14311580	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	14962500	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28782414	1		T1	2		T2	2		T3	5
values[0x0]	245250	1		T1	3		T2	3		T3	2
values[0x1]	246416	1		T1	5		T2	5		T28	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11407036	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	17867044	1		T1	5		T2	5		T3	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	232710	1		T4	113		T24	53		T5	73
valid_sources[0x01]	93259	1		T4	120		T24	34		T5	118
valid_sources[0x02]	107063	1		T30	7		T4	109		T24	33
valid_sources[0x03]	107624	1		T30	7		T4	105		T24	26
valid_sources[0x04]	122816	1		T4	114		T24	32		T5	137
valid_sources[0x05]	92779	1		T4	107		T24	29		T5	108
valid_sources[0x06]	92980	1		T4	104		T24	40		T5	64
valid_sources[0x07]	94289	1		T36	1		T4	151		T24	37
valid_sources[0x08]	109807	1		T29	1		T4	119		T23	1
valid_sources[0x09]	131455	1		T4	119		T24	29		T5	158
valid_sources[0x0a]	91587	1		T30	5		T4	115		T17	1
valid_sources[0x0b]	91856	1		T1	2		T29	2		T4	105
valid_sources[0x0c]	93269	1		T4	109		T24	29		T5	74
valid_sources[0x0d]	91815	1		T4	134		T20	2		T24	46
valid_sources[0x0e]	116986	1		T4	92		T23	1		T24	43
valid_sources[0x0f]	93156	1		T4	137		T22	2		T24	41
valid_sources[0x10]	94682	1		T4	121		T24	34		T5	65
valid_sources[0x11]	92697	1		T4	120		T24	40		T5	80
valid_sources[0x12]	189351	1		T4	115		T24	33		T5	131
valid_sources[0x13]	92855	1		T30	1		T4	111		T24	34
valid_sources[0x14]	92286	1		T28	3		T4	124		T24	36
valid_sources[0x15]	92976	1		T4	119		T24	26		T5	113
valid_sources[0x16]	94456	1		T30	2		T4	147		T24	46
valid_sources[0x17]	93333	1		T4	131		T24	34		T32	1
valid_sources[0x18]	93931	1		T29	1		T30	1		T4	105
valid_sources[0x19]	93018	1		T1	4		T29	1		T4	133
valid_sources[0x1a]	94490	1		T4	95		T24	35		T5	30
valid_sources[0x1b]	116872	1		T29	1		T30	2		T4	99
valid_sources[0x1c]	94347	1		T30	6		T4	103		T24	35
valid_sources[0x1d]	93173	1		T30	11		T4	118		T24	31
valid_sources[0x1e]	92695	1		T30	1		T4	109		T24	43
valid_sources[0x1f]	316440	1		T4	95		T24	30		T5	58
valid_sources[0x20]	93911	1		T4	114		T24	33		T5	178
valid_sources[0x21]	94369	1		T29	1		T30	1		T4	96
valid_sources[0x22]	92301	1		T30	9		T4	102		T24	38
valid_sources[0x23]	138169	1		T30	1		T4	117		T24	31
valid_sources[0x24]	92452	1		T29	1		T4	116		T18	2
valid_sources[0x25]	94287	1		T30	6		T4	122		T24	38
valid_sources[0x26]	92779	1		T4	129		T24	40		T5	68
valid_sources[0x27]	93062	1		T30	4		T4	117		T24	39
valid_sources[0x28]	92645	1		T4	109		T24	38		T5	76
valid_sources[0x29]	95161	1		T4	104		T24	33		T5	79
valid_sources[0x2a]	94441	1		T4	104		T24	26		T5	77
valid_sources[0x2b]	93480	1		T30	4		T4	115		T18	1
valid_sources[0x2c]	113531	1		T4	86		T18	1		T23	2
valid_sources[0x2d]	93436	1		T4	113		T24	43		T5	88
valid_sources[0x2e]	93239	1		T4	128		T24	38		T5	88
valid_sources[0x2f]	149082	1		T4	130		T24	31		T5	50
valid_sources[0x30]	97731	1		T29	1		T4	97		T24	39
valid_sources[0x31]	108365	1		T30	1		T4	109		T18	1
valid_sources[0x32]	92042	1		T4	153		T24	35		T5	102
valid_sources[0x33]	92434	1		T4	119		T24	49		T5	160
valid_sources[0x34]	116181	1		T30	1		T4	117		T24	29
valid_sources[0x35]	95045	1		T4	118		T24	39		T5	128
valid_sources[0x36]	91920	1		T4	114		T24	35		T5	84
valid_sources[0x37]	92271	1		T29	2		T4	120		T24	45
valid_sources[0x38]	93905	1		T29	2		T4	110		T24	33
valid_sources[0x39]	94794	1		T4	96		T24	34		T5	105
valid_sources[0x3a]	93128	1		T4	112		T24	30		T5	49
valid_sources[0x3b]	94301	1		T4	79		T22	1		T24	31
valid_sources[0x3c]	93211	1		T36	2		T4	116		T24	30
valid_sources[0x3d]	97154	1		T4	122		T24	42		T5	84
valid_sources[0x3e]	135621	1		T4	120		T24	31		T5	79
valid_sources[0x3f]	94783	1		T2	3		T30	2		T4	92
valid_sources[0x40]	90973	1		T30	7		T4	114		T17	1
valid_sources[0x41]	93649	1		T4	72		T24	36		T5	87
valid_sources[0x42]	228214	1		T31	13		T4	145		T24	34
valid_sources[0x43]	115357	1		T4	125		T24	39		T5	51
valid_sources[0x44]	145437	1		T4	106		T24	41		T5	99
valid_sources[0x45]	114720	1		T4	126		T24	26		T5	55
valid_sources[0x46]	93366	1		T30	1		T4	113		T24	23
valid_sources[0x47]	94522	1		T4	107		T24	27		T5	82
valid_sources[0x48]	92675	1		T36	1		T4	105		T22	1
valid_sources[0x49]	94311	1		T4	93		T18	1		T23	1
valid_sources[0x4a]	231995	1		T29	1		T4	125		T24	44
valid_sources[0x4b]	91547	1		T28	2		T30	2		T4	89
valid_sources[0x4c]	92597	1		T4	94		T18	1		T24	36
valid_sources[0x4d]	93411	1		T4	110		T24	31		T5	52
valid_sources[0x4e]	208790	1		T4	97		T24	41		T5	105
valid_sources[0x4f]	93697	1		T29	1		T30	7		T4	129
valid_sources[0x50]	91318	1		T4	114		T24	48		T5	89
valid_sources[0x51]	93248	1		T4	108		T18	1		T24	38
valid_sources[0x52]	92248	1		T4	131		T24	47		T5	26
valid_sources[0x53]	93672	1		T30	3		T4	94		T23	1
valid_sources[0x54]	93504	1		T4	123		T24	46		T5	44
valid_sources[0x55]	95577	1		T4	111		T24	37		T5	55
valid_sources[0x56]	91107	1		T4	107		T24	39		T5	92
valid_sources[0x57]	93070	1		T29	2		T30	3		T4	101
valid_sources[0x58]	91534	1		T30	3		T4	116		T24	34
valid_sources[0x59]	185294	1		T29	1		T36	1		T4	124
valid_sources[0x5a]	93690	1		T4	131		T18	1		T24	30
valid_sources[0x5b]	182580	1		T4	119		T24	38		T5	63
valid_sources[0x5c]	93658	1		T30	2		T4	129		T24	22
valid_sources[0x5d]	105166	1		T4	114		T24	39		T5	55
valid_sources[0x5e]	119954	1		T4	128		T18	2		T24	42
valid_sources[0x5f]	92704	1		T30	1		T4	104		T24	36
valid_sources[0x60]	94138	1		T4	113		T24	41		T5	104
valid_sources[0x61]	94090	1		T4	128		T24	42		T5	93
valid_sources[0x62]	233101	1		T4	114		T24	38		T5	115
valid_sources[0x63]	123769	1		T2	1		T30	1		T4	118
valid_sources[0x64]	93370	1		T30	5		T4	118		T18	2
valid_sources[0x65]	92522	1		T29	1		T4	104		T24	40
valid_sources[0x66]	91078	1		T4	142		T24	41		T5	46
valid_sources[0x67]	92695	1		T4	128		T18	1		T24	30
valid_sources[0x68]	94635	1		T4	139		T24	41		T5	37
valid_sources[0x69]	125066	1		T4	94		T18	2		T24	42
valid_sources[0x6a]	93850	1		T4	105		T24	38		T5	64
valid_sources[0x6b]	94784	1		T4	114		T24	35		T5	124
valid_sources[0x6c]	135751	1		T4	115		T24	35		T5	53
valid_sources[0x6d]	121869	1		T4	94		T24	45		T5	41
valid_sources[0x6e]	94882	1		T4	108		T24	36		T5	78
valid_sources[0x6f]	92979	1		T28	6		T4	101		T24	41
valid_sources[0x70]	139977	1		T30	1		T4	124		T24	25
valid_sources[0x71]	180423	1		T35	27		T4	105		T24	39
valid_sources[0x72]	94651	1		T30	2		T4	141		T24	42
valid_sources[0x73]	90437	1		T4	134		T24	30		T5	63
valid_sources[0x74]	124706	1		T29	1		T4	119		T21	10
valid_sources[0x75]	94562	1		T4	105		T24	28		T5	63
valid_sources[0x76]	92028	1		T30	17		T4	129		T24	33
valid_sources[0x77]	93037	1		T30	1		T4	85		T24	49
valid_sources[0x78]	132606	1		T4	127		T24	44		T5	110
valid_sources[0x79]	93362	1		T4	102		T24	33		T32	1
valid_sources[0x7a]	91473	1		T29	2		T4	119		T24	52
valid_sources[0x7b]	91169	1		T4	94		T18	1		T24	36
valid_sources[0x7c]	91865	1		T4	121		T24	46		T5	84
valid_sources[0x7d]	94549	1		T4	116		T24	37		T32	3
valid_sources[0x7e]	297560	1		T30	1		T4	142		T24	22
valid_sources[0x7f]	129493	1		T4	106		T22	1		T24	47
valid_sources[0x80]	92124	1		T30	1		T4	116		T24	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14591797

1

T2

1

T28

2

T29

19

values[0x0]

all_enables

biggest_size

192713

1

T1

2

T2

2

T3

2

values[0x1]

all_enables

biggest_size

177990

1

T1

2

T28

2

T29

2