Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14327189	1		T1	6		T2	7		T3	5
full_word	14963632	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29290521	1		T1	10		T2	10		T3	7
auto[TlIntgErrCmd]	93	1		T214	3		T218	3		T251	7
auto[TlIntgErrData]	107	1		T214	4		T218	4		T251	1
auto[TlIntgErrBoth]	100	1		T214	3		T218	3		T251	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28784429	1		T1	2		T2	2		T3	5
auto[1]	506392	1		T1	8		T2	8		T3	2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14192305	1		T1	2		T2	1		T3	5
auto[TlIntgErrNone]	partial	auto[1]	134619	1		T1	4		T2	6		T28	5
auto[TlIntgErrNone]	full_word	auto[0]	14591998	1		T2	1		T28	2		T29	19
auto[TlIntgErrNone]	full_word	auto[1]	371599	1		T1	4		T2	2		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T218	1		T251	3		T267	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T214	2		T218	2		T251	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T323	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T214	1		T326	1		T327	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T214	1		T218	3		T251	1
auto[TlIntgErrData]	partial	auto[1]	45	1		T214	3		T218	1		T267	1
auto[TlIntgErrData]	full_word	auto[0]	11	1		T301	1		T328	3		T323	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T267	1		T301	1		T329	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T214	1		T218	2		T267	6
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T214	2		T218	1		T251	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T268	1		T328	1		T324	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T251	1		T268	1		T323	1