Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	492063726	12172	0	0
ep_in_enable_rd_A	492063726	2842	0	0
ep_out_enable_rd_A	492063726	2544	0	0
in_iso_rd_A	492063726	2273	0	0
intr_enable_rd_A	492063726	3787	0	0
out_iso_rd_A	492063726	2810	0	0
phy_config_rd_A	492063726	1888	0	0
phy_pins_drive_rd_A	492063726	2184	0	0
rxenable_setup_rd_A	492063726	2530	0	0
set_nak_out_rd_A	492063726	2709	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	12172	0	0
T213	5131	10	0	0
T214	26515	2	0	0
T215	15080	810	0	0
T218	30907	2	0	0
T244	9864	314	0	0
T251	18434	3	0	0
T252	3779	400	0	0
T263	6490	19	0	0
T265	10538	15	0	0
T266	4726	12	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	2842	0	0
T213	5131	50	0	0
T265	10538	10	0	0
T285	4318	5	0	0
T296	10329	29	0	0
T301	22149	323	0	0
T302	40408	159	0	0
T303	11070	37	0	0
T304	3674	2	0	0
T305	5675	14	0	0
T306	5413	9	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	2544	0	0
T213	5131	48	0	0
T265	10538	94	0	0
T285	4318	98	0	0
T296	10329	7	0	0
T301	22149	207	0	0
T302	40408	150	0	0
T303	11070	48	0	0
T305	5675	16	0	0
T306	5413	20	0	0
T307	8470	17	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	2273	0	0
T213	5131	6	0	0
T265	10538	77	0	0
T285	4318	50	0	0
T296	10329	5	0	0
T301	22149	179	0	0
T302	40408	138	0	0
T303	11070	21	0	0
T305	5675	2	0	0
T306	5413	16	0	0
T307	8470	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	3787	0	0
T213	5131	11	0	0
T223	3913	8	0	0
T258	11948	8	0	0
T265	10538	57	0	0
T285	4318	6	0	0
T296	10329	34	0	0
T301	22149	525	0	0
T308	2188	4	0	0
T309	3208	11	0	0
T310	5438	20	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	2810	0	0
T213	5131	37	0	0
T215	15080	4	0	0
T265	10538	43	0	0
T285	4318	76	0	0
T296	10329	9	0	0
T301	22149	276	0	0
T302	40408	161	0	0
T303	11070	27	0	0
T304	3674	6	0	0
T305	5675	13	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	1888	0	0
T213	5131	23	0	0
T265	10538	27	0	0
T285	4318	11	0	0
T296	10329	13	0	0
T301	22149	105	0	0
T302	40408	96	0	0
T303	11070	64	0	0
T304	3674	2	0	0
T305	5675	16	0	0
T306	5413	40	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	2184	0	0
T213	5131	2	0	0
T258	11948	5	0	0
T265	10538	14	0	0
T285	4318	5	0	0
T296	10329	24	0	0
T301	22149	181	0	0
T302	40408	124	0	0
T303	11070	43	0	0
T304	3674	2	0	0
T305	5675	7	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	2530	0	0
T213	5131	51	0	0
T265	10538	101	0	0
T285	4318	46	0	0
T296	10329	27	0	0
T301	22149	166	0	0
T302	40408	112	0	0
T303	11070	42	0	0
T304	3674	2	0	0
T306	5413	34	0	0
T307	8470	42	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492063726	2709	0	0
T213	5131	52	0	0
T265	10538	59	0	0
T285	4318	60	0	0
T296	10329	23	0	0
T301	22149	279	0	0
T302	40408	179	0	0
T303	11070	45	0	0
T304	3674	2	0	0
T305	5675	2	0	0
T306	5413	38	0	0