Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T7,T8,T9 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T7,T8,T9 |
0 |
0 |
1 |
Covered |
T7,T8,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T7,T8,T9 |
0 |
0 |
1 |
Covered |
T7,T8,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
984127452 |
358174 |
0 |
0 |
T4 |
326331 |
0 |
0 |
0 |
T7 |
644324 |
955 |
0 |
0 |
T8 |
0 |
443 |
0 |
0 |
T9 |
0 |
631 |
0 |
0 |
T10 |
0 |
700 |
0 |
0 |
T11 |
0 |
1067 |
0 |
0 |
T12 |
0 |
271 |
0 |
0 |
T13 |
0 |
1410 |
0 |
0 |
T14 |
0 |
714 |
0 |
0 |
T15 |
0 |
532 |
0 |
0 |
T16 |
0 |
488 |
0 |
0 |
T17 |
1548 |
0 |
0 |
0 |
T18 |
9466 |
0 |
0 |
0 |
T19 |
7906 |
0 |
0 |
0 |
T20 |
9145 |
0 |
0 |
0 |
T21 |
8134 |
0 |
0 |
0 |
T22 |
7327 |
0 |
0 |
0 |
T23 |
6977 |
0 |
0 |
0 |
T24 |
845266 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11616424 |
11567312 |
0 |
0 |
T1 |
286 |
274 |
0 |
0 |
T2 |
286 |
266 |
0 |
0 |
T3 |
68 |
48 |
0 |
0 |
T7 |
7354 |
7344 |
0 |
0 |
T28 |
238 |
224 |
0 |
0 |
T29 |
350 |
334 |
0 |
0 |
T30 |
876 |
858 |
0 |
0 |
T31 |
292 |
272 |
0 |
0 |
T35 |
332 |
316 |
0 |
0 |
T36 |
72 |
62 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
984127452 |
1277 |
0 |
0 |
T4 |
326331 |
0 |
0 |
0 |
T7 |
644324 |
2 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T16 |
0 |
2 |
0 |
0 |
T17 |
1548 |
0 |
0 |
0 |
T18 |
9466 |
0 |
0 |
0 |
T19 |
7906 |
0 |
0 |
0 |
T20 |
9145 |
0 |
0 |
0 |
T21 |
8134 |
0 |
0 |
0 |
T22 |
7327 |
0 |
0 |
0 |
T23 |
6977 |
0 |
0 |
0 |
T24 |
845266 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
984127452 |
983618948 |
0 |
0 |
T1 |
15302 |
15128 |
0 |
0 |
T2 |
18012 |
17854 |
0 |
0 |
T3 |
4216 |
4106 |
0 |
0 |
T7 |
1288648 |
1288506 |
0 |
0 |
T28 |
15540 |
15344 |
0 |
0 |
T29 |
18952 |
18768 |
0 |
0 |
T30 |
96828 |
96718 |
0 |
0 |
T31 |
14294 |
14120 |
0 |
0 |
T35 |
17424 |
17310 |
0 |
0 |
T36 |
17756 |
17642 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 16 | 94.12 |
CONT_ASSIGN | 65 | 0 | 0 | |
ALWAYS | 71 | 5 | 4 | 80.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 7 | 7 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
|
unreachable |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
|
unreachable |
75 |
1 |
1 |
76 |
0 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
|
unreachable |
124 |
|
unreachable |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
|
unreachable |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Total | Covered | Percent |
Conditions | 13 | 6 | 46.15 |
Logical | 13 | 6 | 46.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Not Covered | |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
5 |
83.33 |
IF |
71 |
3 |
2 |
66.67 |
IF |
115 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Covered |
T7,T8,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492063726 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5808212 |
5783656 |
0 |
0 |
T1 |
143 |
137 |
0 |
0 |
T2 |
143 |
133 |
0 |
0 |
T3 |
34 |
24 |
0 |
0 |
T7 |
3677 |
3672 |
0 |
0 |
T28 |
119 |
112 |
0 |
0 |
T29 |
175 |
167 |
0 |
0 |
T30 |
438 |
429 |
0 |
0 |
T31 |
146 |
136 |
0 |
0 |
T35 |
166 |
158 |
0 |
0 |
T36 |
36 |
31 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492063726 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492063726 |
491809474 |
0 |
0 |
T1 |
7651 |
7564 |
0 |
0 |
T2 |
9006 |
8927 |
0 |
0 |
T3 |
2108 |
2053 |
0 |
0 |
T7 |
644324 |
644253 |
0 |
0 |
T28 |
7770 |
7672 |
0 |
0 |
T29 |
9476 |
9384 |
0 |
0 |
T30 |
48414 |
48359 |
0 |
0 |
T31 |
7147 |
7060 |
0 |
0 |
T35 |
8712 |
8655 |
0 |
0 |
T36 |
8878 |
8821 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T7,T8,T9 |
0 |
0 |
1 |
Covered |
T7,T8,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T7,T8,T9 |
0 |
0 |
1 |
Covered |
T7,T8,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492063726 |
358174 |
0 |
0 |
T4 |
326331 |
0 |
0 |
0 |
T7 |
644324 |
955 |
0 |
0 |
T8 |
0 |
443 |
0 |
0 |
T9 |
0 |
631 |
0 |
0 |
T10 |
0 |
700 |
0 |
0 |
T11 |
0 |
1067 |
0 |
0 |
T12 |
0 |
271 |
0 |
0 |
T13 |
0 |
1410 |
0 |
0 |
T14 |
0 |
714 |
0 |
0 |
T15 |
0 |
532 |
0 |
0 |
T16 |
0 |
488 |
0 |
0 |
T17 |
1548 |
0 |
0 |
0 |
T18 |
9466 |
0 |
0 |
0 |
T19 |
7906 |
0 |
0 |
0 |
T20 |
9145 |
0 |
0 |
0 |
T21 |
8134 |
0 |
0 |
0 |
T22 |
7327 |
0 |
0 |
0 |
T23 |
6977 |
0 |
0 |
0 |
T24 |
845266 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5808212 |
5783656 |
0 |
0 |
T1 |
143 |
137 |
0 |
0 |
T2 |
143 |
133 |
0 |
0 |
T3 |
34 |
24 |
0 |
0 |
T7 |
3677 |
3672 |
0 |
0 |
T28 |
119 |
112 |
0 |
0 |
T29 |
175 |
167 |
0 |
0 |
T30 |
438 |
429 |
0 |
0 |
T31 |
146 |
136 |
0 |
0 |
T35 |
166 |
158 |
0 |
0 |
T36 |
36 |
31 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492063726 |
1277 |
0 |
0 |
T4 |
326331 |
0 |
0 |
0 |
T7 |
644324 |
2 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T16 |
0 |
2 |
0 |
0 |
T17 |
1548 |
0 |
0 |
0 |
T18 |
9466 |
0 |
0 |
0 |
T19 |
7906 |
0 |
0 |
0 |
T20 |
9145 |
0 |
0 |
0 |
T21 |
8134 |
0 |
0 |
0 |
T22 |
7327 |
0 |
0 |
0 |
T23 |
6977 |
0 |
0 |
0 |
T24 |
845266 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492063726 |
491809474 |
0 |
0 |
T1 |
7651 |
7564 |
0 |
0 |
T2 |
9006 |
8927 |
0 |
0 |
T3 |
2108 |
2053 |
0 |
0 |
T7 |
644324 |
644253 |
0 |
0 |
T28 |
7770 |
7672 |
0 |
0 |
T29 |
9476 |
9384 |
0 |
0 |
T30 |
48414 |
48359 |
0 |
0 |
T31 |
7147 |
7060 |
0 |
0 |
T35 |
8712 |
8655 |
0 |
0 |
T36 |
8878 |
8821 |
0 |
0 |