Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14832596	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15528039	1		T1	16853		T2	30		T3	75317

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29856103	1		T1	33511		T2	65		T3	149843
values[0x0]	251643	1		T1	136		T2	10		T3	239
values[0x1]	252889	1		T1	149		T2	24		T3	261

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11826150	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18534485	1		T1	20267		T2	56		T3	90483

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	92205	1		T1	111		T3	658		T4	67
valid_sources[0x01]	89780	1		T1	110		T2	2		T3	660
valid_sources[0x02]	252522	1		T1	150		T3	567		T4	187
valid_sources[0x03]	139013	1		T1	122		T3	732		T4	66
valid_sources[0x04]	88803	1		T1	141		T3	495		T4	189
valid_sources[0x05]	134981	1		T1	124		T3	692		T4	147
valid_sources[0x06]	89942	1		T1	102		T3	702		T4	123
valid_sources[0x07]	142105	1		T1	78		T2	1		T3	772
valid_sources[0x08]	90570	1		T1	76		T3	654		T4	130
valid_sources[0x09]	89335	1		T1	182		T3	598		T4	104
valid_sources[0x0a]	227621	1		T1	187		T3	801		T4	129
valid_sources[0x0b]	88684	1		T1	116		T3	449		T4	86
valid_sources[0x0c]	88997	1		T1	77		T3	586		T4	103
valid_sources[0x0d]	90747	1		T1	84		T3	486		T4	76
valid_sources[0x0e]	89116	1		T1	122		T2	1		T3	652
valid_sources[0x0f]	89446	1		T1	74		T3	611		T4	133
valid_sources[0x10]	89648	1		T1	103		T3	448		T4	150
valid_sources[0x11]	115668	1		T1	200		T3	551		T4	128
valid_sources[0x12]	103204	1		T1	105		T3	571		T4	74
valid_sources[0x13]	336990	1		T1	190		T3	603		T4	61
valid_sources[0x14]	89430	1		T1	116		T3	471		T4	93
valid_sources[0x15]	88859	1		T1	135		T2	1		T3	608
valid_sources[0x16]	90677	1		T1	126		T3	520		T4	218
valid_sources[0x17]	181095	1		T1	160		T2	3		T3	660
valid_sources[0x18]	287440	1		T1	199		T3	616		T4	65
valid_sources[0x19]	222592	1		T1	90		T2	2		T3	624
valid_sources[0x1a]	89160	1		T1	124		T2	1		T3	706
valid_sources[0x1b]	89149	1		T1	144		T3	547		T4	123
valid_sources[0x1c]	90512	1		T1	96		T3	465		T4	62
valid_sources[0x1d]	90377	1		T1	164		T3	452		T4	209
valid_sources[0x1e]	123450	1		T1	130		T2	6		T3	741
valid_sources[0x1f]	139643	1		T1	172		T3	430		T4	202
valid_sources[0x20]	87640	1		T1	141		T3	582		T4	122
valid_sources[0x21]	90387	1		T1	112		T3	530		T4	70
valid_sources[0x22]	87954	1		T1	132		T3	472		T4	182
valid_sources[0x23]	90085	1		T1	151		T3	496		T4	94
valid_sources[0x24]	228721	1		T1	101		T3	590		T4	113
valid_sources[0x25]	112235	1		T1	146		T2	2		T3	508
valid_sources[0x26]	89732	1		T1	130		T3	488		T4	196
valid_sources[0x27]	90038	1		T1	143		T3	602		T4	165
valid_sources[0x28]	89611	1		T1	185		T2	2		T3	576
valid_sources[0x29]	89390	1		T1	110		T2	2		T3	567
valid_sources[0x2a]	215929	1		T1	153		T3	587		T4	208
valid_sources[0x2b]	112217	1		T1	69		T3	415		T4	81
valid_sources[0x2c]	90786	1		T1	145		T3	547		T4	171
valid_sources[0x2d]	89459	1		T1	166		T3	701		T4	138
valid_sources[0x2e]	89169	1		T1	119		T3	536		T4	107
valid_sources[0x2f]	197791	1		T1	75		T3	585		T4	84
valid_sources[0x30]	90370	1		T1	141		T2	1		T3	685
valid_sources[0x31]	88923	1		T1	115		T3	815		T4	105
valid_sources[0x32]	89587	1		T1	108		T3	483		T4	103
valid_sources[0x33]	89394	1		T1	120		T2	2		T3	599
valid_sources[0x34]	88493	1		T1	165		T2	1		T3	486
valid_sources[0x35]	112388	1		T1	90		T3	642		T4	112
valid_sources[0x36]	132593	1		T1	114		T2	3		T3	437
valid_sources[0x37]	87402	1		T1	129		T2	3		T3	312
valid_sources[0x38]	89675	1		T1	151		T3	696		T4	147
valid_sources[0x39]	91805	1		T1	104		T3	355		T4	103
valid_sources[0x3a]	89110	1		T1	124		T3	541		T4	100
valid_sources[0x3b]	90157	1		T1	115		T3	670		T4	96
valid_sources[0x3c]	88661	1		T1	119		T3	680		T4	145
valid_sources[0x3d]	93520	1		T1	86		T2	1		T3	442
valid_sources[0x3e]	89858	1		T1	110		T3	683		T4	137
valid_sources[0x3f]	138925	1		T1	115		T3	633		T4	109
valid_sources[0x40]	90306	1		T1	92		T3	755		T4	173
valid_sources[0x41]	90486	1		T1	153		T3	431		T4	158
valid_sources[0x42]	93497	1		T1	176		T3	571		T4	190
valid_sources[0x43]	90349	1		T1	110		T2	2		T3	534
valid_sources[0x44]	118448	1		T1	111		T3	671		T4	75
valid_sources[0x45]	90067	1		T1	162		T3	456		T4	139
valid_sources[0x46]	89161	1		T1	170		T3	437		T4	134
valid_sources[0x47]	105757	1		T1	155		T2	3		T3	811
valid_sources[0x48]	89809	1		T1	110		T3	677		T4	149
valid_sources[0x49]	120561	1		T1	194		T3	561		T4	104
valid_sources[0x4a]	108147	1		T1	135		T3	645		T4	117
valid_sources[0x4b]	114839	1		T1	165		T2	2		T3	724
valid_sources[0x4c]	89239	1		T1	160		T3	436		T4	68
valid_sources[0x4d]	127981	1		T1	118		T3	565		T4	142
valid_sources[0x4e]	89229	1		T1	151		T2	1		T3	747
valid_sources[0x4f]	88888	1		T1	117		T3	612		T4	173
valid_sources[0x50]	87648	1		T1	162		T3	482		T4	100
valid_sources[0x51]	89235	1		T1	134		T3	670		T4	33
valid_sources[0x52]	89462	1		T1	177		T2	1		T3	358
valid_sources[0x53]	90960	1		T1	134		T3	619		T4	101
valid_sources[0x54]	121162	1		T1	124		T3	695		T4	181
valid_sources[0x55]	89634	1		T1	155		T3	503		T4	202
valid_sources[0x56]	103134	1		T1	126		T2	1		T3	581
valid_sources[0x57]	90182	1		T1	121		T3	857		T4	94
valid_sources[0x58]	87972	1		T1	153		T2	2		T3	478
valid_sources[0x59]	88801	1		T1	92		T3	615		T4	96
valid_sources[0x5a]	89202	1		T1	70		T2	3		T3	528
valid_sources[0x5b]	89496	1		T1	117		T2	1		T3	421
valid_sources[0x5c]	90017	1		T1	131		T3	576		T36	1
valid_sources[0x5d]	158038	1		T1	92		T3	431		T36	1
valid_sources[0x5e]	198653	1		T1	143		T3	633		T4	96
valid_sources[0x5f]	89447	1		T1	164		T3	555		T4	136
valid_sources[0x60]	90121	1		T1	214		T2	1		T3	640
valid_sources[0x61]	273021	1		T1	145		T2	1		T3	731
valid_sources[0x62]	253266	1		T1	167		T3	476		T4	56
valid_sources[0x63]	89102	1		T1	100		T3	573		T4	154
valid_sources[0x64]	181322	1		T1	99		T3	557		T36	1
valid_sources[0x65]	122753	1		T1	156		T3	461		T4	77
valid_sources[0x66]	207544	1		T1	163		T3	542		T4	115
valid_sources[0x67]	90664	1		T1	137		T3	458		T4	146
valid_sources[0x68]	190151	1		T1	181		T3	792		T4	154
valid_sources[0x69]	94744	1		T1	124		T3	495		T4	153
valid_sources[0x6a]	89645	1		T1	119		T2	1		T3	552
valid_sources[0x6b]	89578	1		T1	137		T2	2		T3	486
valid_sources[0x6c]	90997	1		T1	167		T2	1		T3	708
valid_sources[0x6d]	88684	1		T1	142		T3	512		T4	103
valid_sources[0x6e]	89437	1		T1	151		T3	605		T4	133
valid_sources[0x6f]	173169	1		T1	134		T3	813		T4	108
valid_sources[0x70]	90006	1		T1	164		T3	775		T4	109
valid_sources[0x71]	88688	1		T1	150		T3	691		T4	48
valid_sources[0x72]	89481	1		T1	133		T3	618		T4	269
valid_sources[0x73]	88838	1		T1	122		T3	523		T4	58
valid_sources[0x74]	94189	1		T1	98		T3	509		T4	166
valid_sources[0x75]	89585	1		T1	120		T3	563		T4	184
valid_sources[0x76]	89838	1		T1	159		T3	610		T4	115
valid_sources[0x77]	417875	1		T1	153		T3	560		T4	130
valid_sources[0x78]	203353	1		T1	165		T3	492		T4	144
valid_sources[0x79]	307035	1		T1	96		T3	759		T4	111
valid_sources[0x7a]	88901	1		T1	144		T3	566		T4	105
valid_sources[0x7b]	89859	1		T1	168		T2	3		T3	471
valid_sources[0x7c]	106817	1		T1	73		T2	1		T3	438
valid_sources[0x7d]	167336	1		T1	99		T3	676		T4	239
valid_sources[0x7e]	89056	1		T1	106		T3	500		T4	109
valid_sources[0x7f]	89297	1		T1	94		T2	1		T3	565
valid_sources[0x80]	90800	1		T1	149		T3	611		T4	137

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15147356

1

T1

16655

T2

4

T3

74956

values[0x0]

all_enables

biggest_size

197725

1

T1

102

T2

8

T3

172

values[0x1]

all_enables

biggest_size

182958

1

T1

96

T2

18

T3

189