Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14849654	1		T1	16943		T2	69		T3	75026
full_word	15529229	1		T1	16853		T2	30		T3	75317

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30378593	1		T1	33796		T2	99		T3	150343
auto[TlIntgErrCmd]	102	1		T218	2		T219	1		T250	5
auto[TlIntgErrData]	88	1		T218	4		T219	5		T250	9
auto[TlIntgErrBoth]	100	1		T218	4		T219	4		T250	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29858340	1		T1	33511		T2	65		T3	149843
auto[1]	520543	1		T1	285		T2	34		T3	500

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14710613	1		T1	16856		T2	61		T3	74887
auto[TlIntgErrNone]	partial	auto[1]	138773	1		T1	87		T2	8		T3	139
auto[TlIntgErrNone]	full_word	auto[0]	15147588	1		T1	16655		T2	4		T3	74956
auto[TlIntgErrNone]	full_word	auto[1]	381619	1		T1	198		T2	26		T3	361
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T218	1		T219	1		T250	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T218	1		T250	2		T267	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T267	1		T302	1		T327	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T267	1		T306	1		T327	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T218	3		T219	2		T250	3
auto[TlIntgErrData]	partial	auto[1]	45	1		T218	1		T219	3		T250	4
auto[TlIntgErrData]	full_word	auto[0]	3	1		T250	2		T328	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T267	1		T329	1		T330	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1		T218	3		T219	1		T250	4
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T218	1		T219	3		T250	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T330	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T267	1		T310	1		T331	1