Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	493114846	13905	0	0
ep_in_enable_rd_A	493114846	4549	0	0
ep_out_enable_rd_A	493114846	4736	0	0
in_iso_rd_A	493114846	4742	0	0
intr_enable_rd_A	493114846	6567	0	0
out_iso_rd_A	493114846	4086	0	0
phy_config_rd_A	493114846	2481	0	0
phy_pins_drive_rd_A	493114846	3544	0	0
rxenable_setup_rd_A	493114846	4158	0	0
set_nak_out_rd_A	493114846	4672	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	13905	0	0
T217	14577	709	0	0
T219	12943	3	0	0
T246	5075	889	0	0
T247	6186	639	0	0
T250	32472	6	0	0
T259	10572	15	0	0
T264	10183	21	0	0
T265	4903	7	0	0
T266	3477	9	0	0
T267	84256	6	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	4549	0	0
T259	10572	72	0	0
T264	10183	42	0	0
T277	5011	6	0	0
T300	9629	78	0	0
T301	8339	25	0	0
T302	31154	261	0	0
T303	5821	13	0	0
T304	6218	3	0	0
T305	17902	165	0	0
T306	64193	407	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	4736	0	0
T217	14577	4	0	0
T259	10572	47	0	0
T264	10183	53	0	0
T277	5011	3	0	0
T278	6427	50	0	0
T292	3183	3	0	0
T300	9629	40	0	0
T301	8339	37	0	0
T302	31154	361	0	0
T303	5821	22	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	4742	0	0
T259	10572	106	0	0
T264	10183	66	0	0
T277	5011	24	0	0
T278	6427	66	0	0
T300	9629	51	0	0
T301	8339	19	0	0
T302	31154	332	0	0
T303	5821	45	0	0
T304	6218	9	0	0
T305	17902	217	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	6567	0	0
T227	2790	21	0	0
T229	2569	27	0	0
T259	10572	143	0	0
T264	10183	81	0	0
T292	3183	16	0	0
T300	9629	54	0	0
T301	8339	32	0	0
T307	1669	12	0	0
T308	3293	12	0	0
T309	3324	4	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	4086	0	0
T217	14577	2	0	0
T259	10572	71	0	0
T264	10183	46	0	0
T277	5011	16	0	0
T278	6427	61	0	0
T292	3183	16	0	0
T300	9629	64	0	0
T301	8339	22	0	0
T302	31154	157	0	0
T303	5821	18	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	2481	0	0
T259	10572	18	0	0
T264	10183	30	0	0
T278	6427	21	0	0
T300	9629	52	0	0
T301	8339	38	0	0
T302	31154	94	0	0
T304	6218	4	0	0
T305	17902	200	0	0
T306	64193	288	0	0
T310	22338	44	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	3544	0	0
T259	10572	22	0	0
T260	8344	6	0	0
T264	10183	49	0	0
T277	5011	16	0	0
T278	6427	8	0	0
T292	3183	31	0	0
T300	9629	74	0	0
T301	8339	7	0	0
T302	31154	151	0	0
T303	5821	32	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	4158	0	0
T259	10572	69	0	0
T264	10183	7	0	0
T278	6427	50	0	0
T292	3183	18	0	0
T300	9629	37	0	0
T301	8339	46	0	0
T302	31154	301	0	0
T303	5821	5	0	0
T305	17902	220	0	0
T306	64193	385	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493114846	4672	0	0
T259	10572	49	0	0
T264	10183	75	0	0
T277	5011	30	0	0
T278	6427	49	0	0
T292	3183	3	0	0
T300	9629	39	0	0
T301	8339	24	0	0
T302	31154	212	0	0
T303	5821	37	0	0
T304	6218	7	0	0