Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14136875	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	14810116	1		T1	290		T2	164		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28439047	1		T1	306		T2	175		T3	5
values[0x0]	253618	1		T1	14		T2	39		T3	7
values[0x1]	254326	1		T1	9		T2	38		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11266367	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	17680624	1		T1	292		T2	191		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	84585	1		T1	1		T4	293		T30	55
valid_sources[0x01]	180232	1		T1	1		T4	302		T30	44
valid_sources[0x02]	84465	1		T1	3		T3	1		T4	285
valid_sources[0x03]	83369	1		T1	2		T4	292		T30	78
valid_sources[0x04]	87706	1		T4	275		T30	53		T5	63
valid_sources[0x05]	83211	1		T4	242		T30	46		T5	80
valid_sources[0x06]	203906	1		T1	1		T4	290		T30	57
valid_sources[0x07]	84653	1		T4	281		T30	60		T5	59
valid_sources[0x08]	139794	1		T4	293		T30	40		T5	65
valid_sources[0x09]	85036	1		T1	8		T4	289		T30	83
valid_sources[0x0a]	85991	1		T1	4		T4	281		T30	84
valid_sources[0x0b]	88935	1		T4	299		T30	61		T5	63
valid_sources[0x0c]	84079	1		T1	1		T4	271		T30	72
valid_sources[0x0d]	83728	1		T1	2		T4	290		T30	50
valid_sources[0x0e]	84958	1		T4	248		T30	32		T5	55
valid_sources[0x0f]	83261	1		T1	3		T4	288		T30	45
valid_sources[0x10]	84661	1		T1	1		T4	245		T30	110
valid_sources[0x11]	116838	1		T1	3		T4	299		T30	57
valid_sources[0x12]	84377	1		T4	269		T30	48		T5	60
valid_sources[0x13]	84347	1		T1	4		T4	280		T30	70
valid_sources[0x14]	83996	1		T4	241		T30	57		T5	63
valid_sources[0x15]	172063	1		T4	276		T30	53		T5	70
valid_sources[0x16]	104275	1		T4	306		T30	38		T5	64
valid_sources[0x17]	83300	1		T1	1		T4	268		T30	61
valid_sources[0x18]	83511	1		T1	1		T4	262		T30	47
valid_sources[0x19]	84688	1		T1	1		T4	263		T30	75
valid_sources[0x1a]	86274	1		T4	285		T30	46		T5	78
valid_sources[0x1b]	83986	1		T1	5		T4	267		T30	46
valid_sources[0x1c]	83864	1		T29	1		T4	325		T30	45
valid_sources[0x1d]	84179	1		T4	284		T30	60		T5	70
valid_sources[0x1e]	226163	1		T4	302		T30	87		T5	73
valid_sources[0x1f]	84278	1		T1	2		T4	327		T30	45
valid_sources[0x20]	82806	1		T1	1		T3	3		T4	281
valid_sources[0x21]	199204	1		T4	289		T30	60		T5	71
valid_sources[0x22]	83224	1		T4	244		T30	95		T5	72
valid_sources[0x23]	83020	1		T4	249		T30	36		T5	67
valid_sources[0x24]	83561	1		T1	1		T4	293		T30	68
valid_sources[0x25]	387733	1		T1	3		T4	285		T30	60
valid_sources[0x26]	162816	1		T1	2		T4	315		T30	65
valid_sources[0x27]	82501	1		T4	296		T30	51		T5	60
valid_sources[0x28]	84768	1		T1	3		T4	224		T30	53
valid_sources[0x29]	134825	1		T4	240		T30	46		T5	45
valid_sources[0x2a]	84548	1		T1	2		T4	258		T30	41
valid_sources[0x2b]	106586	1		T4	275		T30	61		T5	62
valid_sources[0x2c]	84395	1		T4	268		T30	57		T5	51
valid_sources[0x2d]	84153	1		T1	2		T4	295		T30	57
valid_sources[0x2e]	85287	1		T4	258		T30	64		T5	65
valid_sources[0x2f]	124118	1		T1	1		T4	307		T30	31
valid_sources[0x30]	83768	1		T4	303		T30	29		T5	74
valid_sources[0x31]	230856	1		T1	1		T4	255		T30	60
valid_sources[0x32]	84735	1		T4	264		T30	66		T5	55
valid_sources[0x33]	82240	1		T1	1		T4	301		T30	51
valid_sources[0x34]	84303	1		T1	2		T4	282		T30	45
valid_sources[0x35]	220426	1		T1	1		T4	285		T30	57
valid_sources[0x36]	83048	1		T4	310		T30	59		T5	68
valid_sources[0x37]	103048	1		T4	310		T30	62		T5	51
valid_sources[0x38]	83785	1		T1	1		T4	276		T30	65
valid_sources[0x39]	103349	1		T1	1		T4	309		T30	71
valid_sources[0x3a]	84327	1		T4	319		T30	58		T5	77
valid_sources[0x3b]	83283	1		T4	248		T30	35		T5	71
valid_sources[0x3c]	145935	1		T1	1		T4	261		T30	61
valid_sources[0x3d]	84720	1		T1	1		T4	264		T30	24
valid_sources[0x3e]	206236	1		T4	363		T30	42		T5	63
valid_sources[0x3f]	84187	1		T1	4		T4	297		T30	59
valid_sources[0x40]	84284	1		T1	2		T4	285		T30	54
valid_sources[0x41]	231873	1		T4	340		T30	38		T5	46
valid_sources[0x42]	86210	1		T1	5		T4	298		T30	55
valid_sources[0x43]	213526	1		T1	4		T4	262		T30	51
valid_sources[0x44]	83286	1		T4	270		T30	44		T5	64
valid_sources[0x45]	218771	1		T4	322		T30	61		T5	57
valid_sources[0x46]	83595	1		T4	251		T30	51		T5	70
valid_sources[0x47]	83894	1		T1	2		T4	289		T30	49
valid_sources[0x48]	99318	1		T1	2		T4	320		T30	59
valid_sources[0x49]	263083	1		T1	4		T4	275		T30	43
valid_sources[0x4a]	84609	1		T4	312		T30	50		T5	76
valid_sources[0x4b]	250068	1		T4	282		T30	53		T5	66
valid_sources[0x4c]	217570	1		T1	1		T4	273		T30	73
valid_sources[0x4d]	112187	1		T1	4		T4	286		T30	55
valid_sources[0x4e]	84414	1		T1	1		T4	283		T30	52
valid_sources[0x4f]	84573	1		T4	282		T30	48		T5	73
valid_sources[0x50]	144485	1		T1	3		T4	272		T30	58
valid_sources[0x51]	83979	1		T4	248		T30	46		T5	73
valid_sources[0x52]	83149	1		T1	1		T4	287		T30	69
valid_sources[0x53]	83661	1		T1	2		T4	285		T30	38
valid_sources[0x54]	84675	1		T4	284		T30	56		T5	62
valid_sources[0x55]	83870	1		T1	1		T4	288		T30	52
valid_sources[0x56]	89975	1		T4	291		T30	49		T5	75
valid_sources[0x57]	100235	1		T1	2		T4	308		T30	49
valid_sources[0x58]	82902	1		T4	287		T30	59		T5	66
valid_sources[0x59]	83423	1		T1	3		T4	260		T30	56
valid_sources[0x5a]	90332	1		T4	290		T30	39		T5	77
valid_sources[0x5b]	84489	1		T4	267		T30	53		T5	77
valid_sources[0x5c]	83329	1		T1	1		T4	263		T30	55
valid_sources[0x5d]	458302	1		T1	4		T4	267		T30	62
valid_sources[0x5e]	84932	1		T4	281		T30	56		T5	58
valid_sources[0x5f]	84774	1		T1	3		T4	305		T30	60
valid_sources[0x60]	84619	1		T1	1		T4	269		T30	64
valid_sources[0x61]	118638	1		T1	2		T4	322		T30	87
valid_sources[0x62]	83109	1		T1	1		T4	292		T30	70
valid_sources[0x63]	119301	1		T1	3		T29	5		T4	301
valid_sources[0x64]	118831	1		T1	4		T4	322		T30	70
valid_sources[0x65]	85097	1		T1	2		T4	309		T30	72
valid_sources[0x66]	97617	1		T1	2		T4	271		T30	46
valid_sources[0x67]	85417	1		T4	261		T30	51		T5	68
valid_sources[0x68]	83184	1		T1	1		T4	302		T30	62
valid_sources[0x69]	192616	1		T1	2		T4	306		T30	41
valid_sources[0x6a]	85592	1		T1	1		T4	322		T30	47
valid_sources[0x6b]	83384	1		T4	255		T30	45		T5	73
valid_sources[0x6c]	169539	1		T1	2		T4	284		T30	73
valid_sources[0x6d]	83233	1		T4	290		T30	84		T5	49
valid_sources[0x6e]	83397	1		T1	1		T4	349		T30	44
valid_sources[0x6f]	118765	1		T1	1		T4	281		T30	36
valid_sources[0x70]	83655	1		T1	2		T4	259		T30	38
valid_sources[0x71]	214769	1		T4	300		T30	50		T5	47
valid_sources[0x72]	84673	1		T1	3		T4	291		T30	54
valid_sources[0x73]	83445	1		T4	328		T30	57		T5	65
valid_sources[0x74]	83558	1		T4	323		T30	34		T5	60
valid_sources[0x75]	85283	1		T4	291		T30	74		T5	67
valid_sources[0x76]	84154	1		T4	294		T30	55		T5	63
valid_sources[0x77]	84421	1		T4	304		T30	52		T5	77
valid_sources[0x78]	85897	1		T4	289		T30	62		T5	72
valid_sources[0x79]	82444	1		T1	1		T4	278		T30	51
valid_sources[0x7a]	83381	1		T1	1		T4	251		T30	75
valid_sources[0x7b]	84129	1		T1	5		T4	281		T30	63
valid_sources[0x7c]	83750	1		T1	4		T4	277		T30	60
valid_sources[0x7d]	84291	1		T1	1		T4	297		T30	39
valid_sources[0x7e]	85653	1		T1	4		T4	304		T30	42
valid_sources[0x7f]	109035	1		T4	336		T30	85		T5	60
valid_sources[0x80]	146300	1		T4	338		T30	59		T5	54

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14426532

1

T1

281

T2

130

T3

1

values[0x0]

all_enables

biggest_size

199606

1

T1

8

T2

22

T3

4

values[0x1]

all_enables

biggest_size

183978

1

T1

1

T2

12

T3

1