Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14153522	1		T1	39		T2	88		T3	10
full_word	14811317	1		T1	290		T2	164		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	28964529	1		T1	329		T2	252		T3	16
auto[TlIntgErrCmd]	112	1		T216	4		T221	2		T247	6
auto[TlIntgErrData]	97	1		T216	2		T221	2		T247	3
auto[TlIntgErrBoth]	101	1		T216	4		T221	6		T247	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28441113	1		T1	306		T2	175		T3	5
auto[1]	523726	1		T1	23		T2	77		T3	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14014243	1		T1	25		T2	45		T3	4
auto[TlIntgErrNone]	partial	auto[1]	138992	1		T1	14		T2	43		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	14426744	1		T1	281		T2	130		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	384550	1		T1	9		T2	34		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T216	2		T247	1		T262	3
auto[TlIntgErrCmd]	partial	auto[1]	70	1		T216	2		T221	2		T247	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T310	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T314	1		T315	1		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1		T216	1		T221	1		T247	1
auto[TlIntgErrData]	partial	auto[1]	44	1		T216	1		T221	1		T247	2
auto[TlIntgErrData]	full_word	auto[0]	7	1		T262	2		T314	1		T316	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T262	1		T317	1		T318	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T216	1		T221	3		T262	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T216	2		T221	3		T262	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T319	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T216	1		T247	1		T262	1