Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	491270878	13172	0	0
ep_in_enable_rd_A	491270878	4070	0	0
ep_out_enable_rd_A	491270878	4306	0	0
in_iso_rd_A	491270878	3689	0	0
intr_enable_rd_A	491270878	5102	0	0
out_iso_rd_A	491270878	3976	0	0
phy_config_rd_A	491270878	2615	0	0
phy_pins_drive_rd_A	491270878	3544	0	0
rxenable_setup_rd_A	491270878	4023	0	0
set_nak_out_rd_A	491270878	4003	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	13172	0	0
T216	28212	4	0	0
T217	2360	9	0	0
T218	3892	28	0	0
T221	16748	3	0	0
T240	6567	11	0	0
T241	3788	274	0	0
T248	9046	568	0	0
T249	5798	5	0	0
T250	5338	702	0	0
T253	7097	323	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	4070	0	0
T216	28212	105	0	0
T254	9145	73	0	0
T257	9253	2	0	0
T258	11360	5	0	0
T278	72900	425	0	0
T288	7258	7	0	0
T289	8434	14	0	0
T292	5116	2	0	0
T294	5486	46	0	0
T297	10916	106	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	4306	0	0
T216	28212	195	0	0
T254	9145	116	0	0
T258	11360	32	0	0
T276	6775	21	0	0
T278	72900	457	0	0
T288	7258	4	0	0
T289	8434	7	0	0
T292	5116	14	0	0
T294	5486	41	0	0
T297	10916	99	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	3689	0	0
T216	28212	168	0	0
T254	9145	64	0	0
T258	11360	23	0	0
T276	6775	28	0	0
T278	72900	455	0	0
T289	8434	4	0	0
T292	5116	26	0	0
T294	5486	26	0	0
T295	8946	4	0	0
T297	10916	82	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	5102	0	0
T216	28212	170	0	0
T226	3643	10	0	0
T254	9145	20	0	0
T258	11360	53	0	0
T276	6775	56	0	0
T278	72900	433	0	0
T288	7258	14	0	0
T289	8434	7	0	0
T292	5116	12	0	0
T297	10916	117	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	3976	0	0
T216	28212	169	0	0
T254	9145	122	0	0
T258	11360	37	0	0
T276	6775	32	0	0
T278	72900	451	0	0
T288	7258	15	0	0
T289	8434	1	0	0
T292	5116	25	0	0
T294	5486	17	0	0
T297	10916	92	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	2615	0	0
T216	28212	96	0	0
T254	9145	59	0	0
T258	11360	17	0	0
T276	6775	7	0	0
T278	72900	399	0	0
T288	7258	16	0	0
T292	5116	8	0	0
T294	5486	43	0	0
T295	8946	28	0	0
T297	10916	89	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	3544	0	0
T216	28212	105	0	0
T254	9145	70	0	0
T258	11360	32	0	0
T276	6775	7	0	0
T278	72900	488	0	0
T288	7258	22	0	0
T289	8434	61	0	0
T292	5116	27	0	0
T294	5486	15	0	0
T297	10916	115	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	4023	0	0
T216	28212	83	0	0
T254	9145	60	0	0
T258	11360	38	0	0
T278	72900	428	0	0
T288	7258	9	0	0
T289	8434	18	0	0
T292	5116	19	0	0
T294	5486	15	0	0
T295	8946	5	0	0
T297	10916	83	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491270878	4003	0	0
T216	28212	89	0	0
T254	9145	16	0	0
T258	11360	20	0	0
T276	6775	31	0	0
T278	72900	441	0	0
T288	7258	4	0	0
T289	8434	9	0	0
T292	5116	3	0	0
T294	5486	4	0	0
T297	10916	112	0	0