Line Coverage for Module :
prim_generic_ram_1p
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
42 |
0 |
1 |
52 |
|
unreachable |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
67 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Module :
prim_generic_ram_1p
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
IF |
63 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 63 if (req_i)
-2-: 64 if (write_i)
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_generic_ram_1p
Assertion Details
DataBitsPerMaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2634 |
2634 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T35 |
1 |
1 |
0 |
0 |
gen_wmask[0].MaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489354263 |
973078 |
0 |
0 |
T1 |
54005 |
256 |
0 |
0 |
T2 |
50001 |
131 |
0 |
0 |
T3 |
8286 |
2 |
0 |
0 |
T4 |
703942 |
492 |
0 |
0 |
T5 |
181704 |
521 |
0 |
0 |
T6 |
290321 |
841 |
0 |
0 |
T29 |
7064 |
0 |
0 |
0 |
T30 |
399163 |
11680 |
0 |
0 |
T31 |
7869 |
0 |
0 |
0 |
T32 |
0 |
908 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T34 |
0 |
14 |
0 |
0 |
T35 |
2811 |
0 |
0 |
0 |
gen_wmask[1].MaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489354263 |
973078 |
0 |
0 |
T1 |
54005 |
256 |
0 |
0 |
T2 |
50001 |
131 |
0 |
0 |
T3 |
8286 |
2 |
0 |
0 |
T4 |
703942 |
492 |
0 |
0 |
T5 |
181704 |
521 |
0 |
0 |
T6 |
290321 |
841 |
0 |
0 |
T29 |
7064 |
0 |
0 |
0 |
T30 |
399163 |
11680 |
0 |
0 |
T31 |
7869 |
0 |
0 |
0 |
T32 |
0 |
908 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T34 |
0 |
14 |
0 |
0 |
T35 |
2811 |
0 |
0 |
0 |
gen_wmask[2].MaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489354263 |
973078 |
0 |
0 |
T1 |
54005 |
256 |
0 |
0 |
T2 |
50001 |
131 |
0 |
0 |
T3 |
8286 |
2 |
0 |
0 |
T4 |
703942 |
492 |
0 |
0 |
T5 |
181704 |
521 |
0 |
0 |
T6 |
290321 |
841 |
0 |
0 |
T29 |
7064 |
0 |
0 |
0 |
T30 |
399163 |
11680 |
0 |
0 |
T31 |
7869 |
0 |
0 |
0 |
T32 |
0 |
908 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T34 |
0 |
14 |
0 |
0 |
T35 |
2811 |
0 |
0 |
0 |
gen_wmask[3].MaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489354263 |
973078 |
0 |
0 |
T1 |
54005 |
256 |
0 |
0 |
T2 |
50001 |
131 |
0 |
0 |
T3 |
8286 |
2 |
0 |
0 |
T4 |
703942 |
492 |
0 |
0 |
T5 |
181704 |
521 |
0 |
0 |
T6 |
290321 |
841 |
0 |
0 |
T29 |
7064 |
0 |
0 |
0 |
T30 |
399163 |
11680 |
0 |
0 |
T31 |
7869 |
0 |
0 |
0 |
T32 |
0 |
908 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T34 |
0 |
14 |
0 |
0 |
T35 |
2811 |
0 |
0 |
0 |