Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	359	1		T2	8		T7	8		T9	5
all_values[1]	359	1		T2	8		T7	8		T9	5
all_values[2]	359	1		T2	8		T7	8		T9	5
all_values[3]	359	1		T2	8		T7	8		T9	5
all_values[4]	359	1		T2	8		T7	8		T9	5
all_values[5]	359	1		T2	8		T7	8		T9	5
all_values[6]	359	1		T2	8		T7	8		T9	5
all_values[7]	359	1		T2	8		T7	8		T9	5
all_values[8]	359	1		T2	8		T7	8		T9	5
all_values[9]	359	1		T2	8		T7	8		T9	5
all_values[10]	359	1		T2	8		T7	8		T9	5
all_values[11]	359	1		T2	8		T7	8		T9	5
all_values[12]	359	1		T2	8		T7	8		T9	5
all_values[13]	359	1		T2	8		T7	8		T9	5
all_values[14]	359	1		T2	8		T7	8		T9	5
all_values[15]	359	1		T2	8		T7	8		T9	5
all_values[16]	359	1		T2	8		T7	8		T9	5
all_values[17]	359	1		T2	8		T7	8		T9	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3587	1		T2	88		T7	73		T9	41
auto[1]	2875	1		T2	56		T7	71		T9	49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1629	1		T2	17		T7	7		T9	24
auto[1]	4833	1		T2	127		T7	137		T9	66

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	58	1		T2	1		T9	5		T8	2
all_values[0]	auto[0]	auto[1]	131	1		T2	5		T7	3		T8	4
all_values[0]	auto[1]	auto[0]	32	1		T8	2		T35	1		T71	4
all_values[0]	auto[1]	auto[1]	138	1		T2	2		T7	5		T13	6
all_values[1]	auto[0]	auto[0]	72	1		T2	1		T16	2		T18	2
all_values[1]	auto[0]	auto[1]	123	1		T2	4		T7	6		T9	1
all_values[1]	auto[1]	auto[0]	14	1		T71	1		T75	1		T76	1
all_values[1]	auto[1]	auto[1]	150	1		T2	3		T7	2		T9	4
all_values[2]	auto[0]	auto[0]	67	1		T9	1		T13	1		T16	2
all_values[2]	auto[0]	auto[1]	125	1		T2	4		T7	2		T9	4
all_values[2]	auto[1]	auto[0]	24	1		T7	1		T13	1		T32	1
all_values[2]	auto[1]	auto[1]	143	1		T2	4		T7	5		T8	5
all_values[3]	auto[0]	auto[0]	57	1		T2	1		T13	1		T16	2
all_values[3]	auto[0]	auto[1]	140	1		T2	1		T7	7		T8	3
all_values[3]	auto[1]	auto[0]	25	1		T2	3		T34	1		T43	1
all_values[3]	auto[1]	auto[1]	137	1		T2	3		T7	1		T9	5
all_values[4]	auto[0]	auto[0]	72	1		T9	1		T8	1		T16	2
all_values[4]	auto[0]	auto[1]	130	1		T2	4		T7	2		T9	3
all_values[4]	auto[1]	auto[0]	31	1		T8	1		T13	2		T71	4
all_values[4]	auto[1]	auto[1]	126	1		T2	4		T7	6		T9	1
all_values[5]	auto[0]	auto[0]	69	1		T8	2		T16	2		T18	2
all_values[5]	auto[0]	auto[1]	128	1		T2	2		T7	6		T9	3
all_values[5]	auto[1]	auto[0]	25	1		T8	3		T34	1		T35	1
all_values[5]	auto[1]	auto[1]	137	1		T2	6		T7	2		T9	2
all_values[6]	auto[0]	auto[0]	55	1		T9	1		T13	1		T16	2
all_values[6]	auto[0]	auto[1]	142	1		T2	6		T7	7		T8	2
all_values[6]	auto[1]	auto[0]	32	1		T2	1		T8	1		T13	1
all_values[6]	auto[1]	auto[1]	130	1		T2	1		T7	1		T9	4
all_values[7]	auto[0]	auto[0]	61	1		T2	2		T13	1		T16	2
all_values[7]	auto[0]	auto[1]	145	1		T7	5		T9	3		T8	4
all_values[7]	auto[1]	auto[0]	18	1		T2	2		T9	2		T45	2
all_values[7]	auto[1]	auto[1]	135	1		T2	4		T7	3		T8	4
all_values[8]	auto[0]	auto[0]	75	1		T9	1		T16	2		T18	2
all_values[8]	auto[0]	auto[1]	123	1		T2	6		T7	2		T9	1
all_values[8]	auto[1]	auto[0]	20	1		T32	1		T71	5		T72	1
all_values[8]	auto[1]	auto[1]	141	1		T2	2		T7	6		T9	3
all_values[9]	auto[0]	auto[0]	69	1		T9	1		T16	2		T18	2
all_values[9]	auto[0]	auto[1]	124	1		T2	2		T7	3		T8	3
all_values[9]	auto[1]	auto[0]	36	1		T7	1		T9	4		T8	1
all_values[9]	auto[1]	auto[1]	130	1		T2	6		T7	4		T8	4
all_values[10]	auto[0]	auto[0]	62	1		T16	2		T18	2		T19	2
all_values[10]	auto[0]	auto[1]	113	1		T2	6		T7	2		T8	1
all_values[10]	auto[1]	auto[0]	24	1		T32	2		T35	1		T72	5
all_values[10]	auto[1]	auto[1]	160	1		T2	2		T7	6		T9	5
all_values[11]	auto[0]	auto[0]	74	1		T9	1		T16	2		T18	2
all_values[11]	auto[0]	auto[1]	140	1		T2	5		T7	4		T9	3
all_values[11]	auto[1]	auto[0]	22	1		T7	1		T13	1		T35	1
all_values[11]	auto[1]	auto[1]	123	1		T2	3		T7	3		T9	1
all_values[12]	auto[0]	auto[0]	77	1		T2	1		T16	2		T18	2
all_values[12]	auto[0]	auto[1]	125	1		T2	5		T7	5		T9	4
all_values[12]	auto[1]	auto[0]	16	1		T2	1		T35	1		T76	1
all_values[12]	auto[1]	auto[1]	141	1		T2	1		T7	3		T9	1
all_values[13]	auto[0]	auto[0]	62	1		T2	1		T16	2		T18	2
all_values[13]	auto[0]	auto[1]	134	1		T2	7		T7	6		T9	1
all_values[13]	auto[1]	auto[0]	19	1		T41	1		T47	1		T77	2
all_values[13]	auto[1]	auto[1]	144	1		T7	2		T9	4		T13	3
all_values[14]	auto[0]	auto[0]	68	1		T8	1		T16	2		T18	2
all_values[14]	auto[0]	auto[1]	146	1		T2	5		T7	1		T9	3
all_values[14]	auto[1]	auto[0]	24	1		T7	2		T9	1		T8	1
all_values[14]	auto[1]	auto[1]	121	1		T2	3		T7	5		T9	1
all_values[15]	auto[0]	auto[0]	61	1		T9	1		T16	2		T18	2
all_values[15]	auto[0]	auto[1]	157	1		T2	5		T7	6		T8	1
all_values[15]	auto[1]	auto[0]	23	1		T2	1		T7	2		T8	1
all_values[15]	auto[1]	auto[1]	118	1		T2	2		T9	4		T8	6
all_values[16]	auto[0]	auto[0]	62	1		T2	1		T9	1		T13	1
all_values[16]	auto[0]	auto[1]	136	1		T2	6		T7	1		T8	5
all_values[16]	auto[1]	auto[0]	33	1		T2	1		T9	4		T8	1
all_values[16]	auto[1]	auto[1]	128	1		T7	7		T8	2		T13	1
all_values[17]	auto[0]	auto[0]	57	1		T16	2		T18	2		T19	2
all_values[17]	auto[0]	auto[1]	147	1		T2	7		T7	5		T9	2
all_values[17]	auto[1]	auto[0]	33	1		T13	1		T71	2		T45	3
all_values[17]	auto[1]	auto[1]	122	1		T2	1		T7	3		T9	3