| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 67.90 | 65.32 | 59.60 | 86.57 | 0.00 | 69.84 | 97.77 | 96.22 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 55.10 | 55.10 | 62.19 | 62.19 | 49.27 | 49.27 | 84.27 | 84.27 | 0.00 | 0.00 | 63.17 | 63.17 | 92.18 | 92.18 | 34.59 | 34.59 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.704622342 |
| 62.40 | 7.30 | 62.89 | 0.70 | 50.80 | 1.54 | 89.91 | 5.63 | 0.00 | 0.00 | 63.33 | 0.16 | 92.18 | 0.00 | 77.66 | 43.06 | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1569926655 |
| 64.79 | 2.40 | 65.24 | 2.35 | 56.25 | 5.45 | 91.08 | 1.17 | 0.00 | 0.00 | 69.76 | 6.43 | 93.58 | 1.40 | 77.66 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.825382509 |
| 66.12 | 1.33 | 65.32 | 0.08 | 58.32 | 2.07 | 93.19 | 2.11 | 0.00 | 0.00 | 69.84 | 0.08 | 96.37 | 2.79 | 79.82 | 2.16 | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2390322916 |
| 67.31 | 1.19 | 65.32 | 0.00 | 58.32 | 0.00 | 93.43 | 0.23 | 0.00 | 0.00 | 69.84 | 0.00 | 96.37 | 0.00 | 87.93 | 8.11 | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2836933703 |
| 67.88 | 0.57 | 65.32 | 0.00 | 58.32 | 0.00 | 93.43 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 96.37 | 0.00 | 91.89 | 3.96 | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4136565993 |
| 68.13 | 0.25 | 65.32 | 0.00 | 59.37 | 1.05 | 93.43 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 96.37 | 0.00 | 92.61 | 0.72 | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.941532584 |
| 68.37 | 0.23 | 65.32 | 0.00 | 59.37 | 0.00 | 95.07 | 1.64 | 0.00 | 0.00 | 69.84 | 0.00 | 96.37 | 0.00 | 92.61 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3328022048 |
| 68.54 | 0.17 | 65.32 | 0.00 | 59.37 | 0.00 | 95.07 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 96.65 | 0.28 | 93.51 | 0.90 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2505362294 |
| 68.69 | 0.15 | 65.32 | 0.00 | 59.37 | 0.00 | 95.07 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 96.65 | 0.00 | 94.59 | 1.08 | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.983528976 |
| 68.83 | 0.14 | 65.32 | 0.00 | 59.48 | 0.12 | 95.07 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.49 | 0.84 | 94.59 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.639964256 |
| 68.94 | 0.11 | 65.32 | 0.00 | 59.48 | 0.00 | 95.31 | 0.23 | 0.00 | 0.00 | 69.84 | 0.00 | 97.49 | 0.00 | 95.14 | 0.54 | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.761135901 |
| 68.99 | 0.05 | 65.32 | 0.00 | 59.48 | 0.00 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.49 | 0.00 | 95.50 | 0.36 | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4287981532 |
| 69.04 | 0.05 | 65.32 | 0.00 | 59.48 | 0.00 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.49 | 0.00 | 95.86 | 0.36 | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1233366839 |
| 69.08 | 0.04 | 65.32 | 0.00 | 59.48 | 0.00 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.28 | 95.86 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4016022906 |
| 69.11 | 0.03 | 65.32 | 0.00 | 59.51 | 0.02 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.04 | 0.18 | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4223956150 |
| 69.14 | 0.03 | 65.32 | 0.00 | 59.51 | 0.00 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.22 | 0.18 | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.509828836 |
| 69.15 | 0.01 | 65.32 | 0.00 | 59.58 | 0.07 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4294070866 |
| 69.15 | 0.01 | 65.32 | 0.00 | 59.60 | 0.02 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4124530498 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2296047275 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2764973329 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.906316804 |
| /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3783114408 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2803991627 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1796577757 |
| /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2545465183 |
| /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1402591427 |
| /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1056541897 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1926684585 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1135533451 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1733785233 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1896344851 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1474570329 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1129760976 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.62506528 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2758233856 |
| /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1605152938 |
| /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3087494445 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2594120173 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1815108629 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2301554407 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.162249845 |
| /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3337750518 |
| /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2927598535 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3788041939 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1463173473 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.574293990 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3680328044 |
| /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2619797196 |
| /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.188280878 |
| /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3849450467 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2307446807 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3391482292 |
| /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2266688962 |
| /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3054103663 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3865973234 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1737273295 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.954907930 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4255441661 |
| /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.600837467 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3310607262 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.894647842 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1793846955 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1668248294 |
| /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1499010237 |
| /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1856678158 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1522074175 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1357325273 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.514668303 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.419781628 |
| /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1760180180 |
| /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1493649607 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3436346640 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3026604698 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3059052051 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2703822335 |
| /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3377612276 |
| /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2363740525 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.368186719 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2717136109 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1364540767 |
| /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2381306197 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3702747495 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1931900470 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.679121468 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3276606084 |
| /workspace/coverage/cover_reg_top/19.usbdev_intr_test.774902582 |
| /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1239412719 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2766736269 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2848202252 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.204062099 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.184521023 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.676823651 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3175699621 |
| /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1727851207 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3059434276 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.704453795 |
| /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1955630037 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2560256651 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.822987895 |
| /workspace/coverage/cover_reg_top/20.usbdev_intr_test.622736825 |
| /workspace/coverage/cover_reg_top/21.usbdev_intr_test.761155409 |
| /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2951078646 |
| /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2627779382 |
| /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3049820063 |
| /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1498515579 |
| /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4087829227 |
| /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4130451859 |
| /workspace/coverage/cover_reg_top/28.usbdev_intr_test.827958866 |
| /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3131769937 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.89802991 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3816801525 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1230196560 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.501217388 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.431102401 |
| /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1813670584 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2755146118 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3110565860 |
| /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2304395751 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2447385885 |
| /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3047924250 |
| /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3576483282 |
| /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3641691936 |
| /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4211910282 |
| /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3229541432 |
| /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3871901568 |
| /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2714564187 |
| /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3620278417 |
| /workspace/coverage/cover_reg_top/39.usbdev_intr_test.680697688 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1403083313 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1253856767 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1970464000 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2390247311 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3196219759 |
| /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4224631024 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1431218926 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3929723266 |
| /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3616798699 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2482332866 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2170876648 |
| /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4220452766 |
| /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2244184791 |
| /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1420216221 |
| /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3796722323 |
| /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2299410200 |
| /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4278949654 |
| /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3150766890 |
| /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2286346547 |
| /workspace/coverage/cover_reg_top/49.usbdev_intr_test.477648254 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1336574212 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.342777846 |
| /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3085246279 |
| /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1462579400 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2816509527 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2317571737 |
| /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3319729921 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1467021312 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3176445232 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.690429652 |
| /workspace/coverage/cover_reg_top/7.usbdev_intr_test.297615399 |
| /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3492365 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1169650806 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.62659258 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2413252695 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3938774373 |
| /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2407341465 |
| /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.976172351 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1283430642 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.47686961 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3947646322 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2302830677 |
| /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3708510849 |
| /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.144499821 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4122433504 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2557096237 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.639964256 | Jul 05 04:37:39 PM PDT 24 | Jul 05 04:37:42 PM PDT 24 | 227136412 ps | ||
| T2 | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4211910282 | Jul 05 04:37:55 PM PDT 24 | Jul 05 04:37:58 PM PDT 24 | 33415371 ps | ||
| T3 | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.204062099 | Jul 05 04:37:52 PM PDT 24 | Jul 05 04:37:58 PM PDT 24 | 370184923 ps | ||
| T4 | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2717136109 | Jul 05 04:37:51 PM PDT 24 | Jul 05 04:37:55 PM PDT 24 | 180309607 ps | ||
| T7 | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3049820063 | Jul 05 04:37:56 PM PDT 24 | Jul 05 04:37:59 PM PDT 24 | 77304521 ps | ||
| T9 | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2714564187 | Jul 05 04:38:01 PM PDT 24 | Jul 05 04:38:05 PM PDT 24 | 39994168 ps | ||
| T8 | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.774902582 | Jul 05 04:37:47 PM PDT 24 | Jul 05 04:37:50 PM PDT 24 | 71605534 ps | ||
| T5 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.704622342 | Jul 05 04:37:37 PM PDT 24 | Jul 05 04:37:43 PM PDT 24 | 1666720957 ps | ||
| T6 | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1793846955 | Jul 05 04:37:45 PM PDT 24 | Jul 05 04:37:50 PM PDT 24 | 102144007 ps | ||
| T14 | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2848202252 | Jul 05 04:37:56 PM PDT 24 | Jul 05 04:38:00 PM PDT 24 | 191746529 ps | ||
| T15 | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.954907930 | Jul 05 04:38:02 PM PDT 24 | Jul 05 04:38:08 PM PDT 24 | 126078708 ps | ||
| T13 | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1569926655 | Jul 05 04:37:50 PM PDT 24 | Jul 05 04:37:53 PM PDT 24 | 79487944 ps | ||
| T16 | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2447385885 | Jul 05 04:37:39 PM PDT 24 | Jul 05 04:37:43 PM PDT 24 | 257040723 ps | ||
| T24 | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3175699621 | Jul 05 04:37:33 PM PDT 24 | Jul 05 04:37:35 PM PDT 24 | 88130654 ps | ||
| T17 | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2390322916 | Jul 05 04:37:55 PM PDT 24 | Jul 05 04:37:59 PM PDT 24 | 181419441 ps | ||
| T18 | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.941532584 | Jul 05 04:37:55 PM PDT 24 | Jul 05 04:38:01 PM PDT 24 | 269568494 ps | ||
| T19 | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1522074175 | Jul 05 04:37:46 PM PDT 24 | Jul 05 04:37:52 PM PDT 24 | 322465246 ps | ||
| T32 | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1760180180 | Jul 05 04:38:01 PM PDT 24 | Jul 05 04:38:05 PM PDT 24 | 48726550 ps | ||
| T25 | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.906316804 | Jul 05 04:37:24 PM PDT 24 | Jul 05 04:37:31 PM PDT 24 | 84434996 ps | ||
| T20 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3849450467 | Jul 05 04:37:56 PM PDT 24 | Jul 05 04:38:00 PM PDT 24 | 85520520 ps | ||
| T33 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.600837467 | Jul 05 04:38:03 PM PDT 24 | Jul 05 04:38:09 PM PDT 24 | 135251951 ps | ||
| T34 | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3708510849 | Jul 05 04:37:48 PM PDT 24 | Jul 05 04:37:51 PM PDT 24 | 39799527 ps | ||
| T35 | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2836933703 | Jul 05 04:37:45 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 30907455 ps | ||
| T23 | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.822987895 | Jul 05 04:37:31 PM PDT 24 | Jul 05 04:37:36 PM PDT 24 | 490764379 ps | ||
| T79 | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4278949654 | Jul 05 04:38:05 PM PDT 24 | Jul 05 04:38:10 PM PDT 24 | 31915053 ps | ||
| T21 | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.514668303 | Jul 05 04:37:56 PM PDT 24 | Jul 05 04:37:59 PM PDT 24 | 89934056 ps | ||
| T56 | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3054103663 | Jul 05 04:37:54 PM PDT 24 | Jul 05 04:37:57 PM PDT 24 | 93795715 ps | ||
| T57 | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.144499821 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:47 PM PDT 24 | 66568582 ps | ||
| T26 | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1896344851 | Jul 05 04:37:53 PM PDT 24 | Jul 05 04:37:56 PM PDT 24 | 157515518 ps | ||
| T22 | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.501217388 | Jul 05 04:37:39 PM PDT 24 | Jul 05 04:37:42 PM PDT 24 | 88175521 ps | ||
| T71 | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.761155409 | Jul 05 04:37:52 PM PDT 24 | Jul 05 04:37:55 PM PDT 24 | 47374147 ps | ||
| T63 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4294070866 | Jul 05 04:37:47 PM PDT 24 | Jul 05 04:37:53 PM PDT 24 | 124470375 ps | ||
| T72 | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4287981532 | Jul 05 04:37:39 PM PDT 24 | Jul 05 04:37:41 PM PDT 24 | 44130989 ps | ||
| T65 | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1733785233 | Jul 05 04:37:30 PM PDT 24 | Jul 05 04:37:34 PM PDT 24 | 111811113 ps | ||
| T27 | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1856678158 | Jul 05 04:38:02 PM PDT 24 | Jul 05 04:38:08 PM PDT 24 | 174345530 ps | ||
| T28 | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1364540767 | Jul 05 04:37:45 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 107860985 ps | ||
| T29 | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.162249845 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 80138880 ps | ||
| T89 | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1336574212 | Jul 05 04:37:37 PM PDT 24 | Jul 05 04:37:39 PM PDT 24 | 86171663 ps | ||
| T62 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.894647842 | Jul 05 04:37:43 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 431725657 ps | ||
| T90 | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3929723266 | Jul 05 04:37:40 PM PDT 24 | Jul 05 04:37:45 PM PDT 24 | 521650143 ps | ||
| T30 | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.89802991 | Jul 05 04:37:38 PM PDT 24 | Jul 05 04:37:42 PM PDT 24 | 231343349 ps | ||
| T91 | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3110565860 | Jul 05 04:37:37 PM PDT 24 | Jul 05 04:37:42 PM PDT 24 | 219859290 ps | ||
| T92 | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2363740525 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 95567327 ps | ||
| T93 | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2381306197 | Jul 05 04:38:06 PM PDT 24 | Jul 05 04:38:11 PM PDT 24 | 97495935 ps | ||
| T31 | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1431218926 | Jul 05 04:37:41 PM PDT 24 | Jul 05 04:37:44 PM PDT 24 | 81566421 ps | ||
| T40 | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3059052051 | Jul 05 04:37:48 PM PDT 24 | Jul 05 04:37:52 PM PDT 24 | 162598162 ps | ||
| T41 | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3377612276 | Jul 05 04:37:54 PM PDT 24 | Jul 05 04:37:56 PM PDT 24 | 40746326 ps | ||
| T42 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2482332866 | Jul 05 04:37:37 PM PDT 24 | Jul 05 04:37:42 PM PDT 24 | 379627173 ps | ||
| T43 | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3641691936 | Jul 05 04:37:57 PM PDT 24 | Jul 05 04:38:01 PM PDT 24 | 60394370 ps | ||
| T44 | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2766736269 | Jul 05 04:38:03 PM PDT 24 | Jul 05 04:38:10 PM PDT 24 | 177145473 ps | ||
| T45 | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4136565993 | Jul 05 04:38:02 PM PDT 24 | Jul 05 04:38:06 PM PDT 24 | 55736104 ps | ||
| T46 | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.62659258 | Jul 05 04:37:55 PM PDT 24 | Jul 05 04:38:03 PM PDT 24 | 1228948349 ps | ||
| T47 | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4130451859 | Jul 05 04:38:02 PM PDT 24 | Jul 05 04:38:07 PM PDT 24 | 66719730 ps | ||
| T48 | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.477648254 | Jul 05 04:37:59 PM PDT 24 | Jul 05 04:38:02 PM PDT 24 | 50944415 ps | ||
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| T66 | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3176445232 | Jul 05 04:37:45 PM PDT 24 | Jul 05 04:37:49 PM PDT 24 | 106570695 ps | ||
| T74 | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3865973234 | Jul 05 04:37:55 PM PDT 24 | Jul 05 04:37:59 PM PDT 24 | 216348389 ps | ||
| T11 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.825382509 | Jul 05 04:37:48 PM PDT 24 | Jul 05 04:37:51 PM PDT 24 | 130520260 ps | ||
| T94 | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2545465183 | Jul 05 04:37:39 PM PDT 24 | Jul 05 04:37:42 PM PDT 24 | 114331907 ps | ||
| T69 | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1169650806 | Jul 05 04:37:54 PM PDT 24 | Jul 05 04:38:00 PM PDT 24 | 360175705 ps | ||
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| T67 | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3492365 | Jul 05 04:37:47 PM PDT 24 | Jul 05 04:37:51 PM PDT 24 | 212822437 ps | ||
| T95 | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2927598535 | Jul 05 04:37:52 PM PDT 24 | Jul 05 04:37:56 PM PDT 24 | 109696764 ps | ||
| T75 | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.761135901 | Jul 05 04:37:51 PM PDT 24 | Jul 05 04:37:54 PM PDT 24 | 51838981 ps | ||
| T96 | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1129760976 | Jul 05 04:37:39 PM PDT 24 | Jul 05 04:37:43 PM PDT 24 | 111671303 ps | ||
| T60 | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4223956150 | Jul 05 04:37:53 PM PDT 24 | Jul 05 04:37:59 PM PDT 24 | 742668192 ps | ||
| T97 | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2619797196 | Jul 05 04:38:04 PM PDT 24 | Jul 05 04:38:08 PM PDT 24 | 48005733 ps | ||
| T98 | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1283430642 | Jul 05 04:37:58 PM PDT 24 | Jul 05 04:38:03 PM PDT 24 | 138114479 ps | ||
| T99 | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.690429652 | Jul 05 04:37:46 PM PDT 24 | Jul 05 04:37:49 PM PDT 24 | 63344955 ps | ||
| T100 | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.574293990 | Jul 05 04:37:56 PM PDT 24 | Jul 05 04:37:59 PM PDT 24 | 55251607 ps | ||
| T101 | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3131769937 | Jul 05 04:37:58 PM PDT 24 | Jul 05 04:38:01 PM PDT 24 | 77669202 ps | ||
| T68 | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2307446807 | Jul 05 04:37:52 PM PDT 24 | Jul 05 04:37:56 PM PDT 24 | 108169628 ps | ||
| T102 | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.188280878 | Jul 05 04:37:50 PM PDT 24 | Jul 05 04:37:54 PM PDT 24 | 200210205 ps | ||
| T84 | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2557096237 | Jul 05 04:37:42 PM PDT 24 | Jul 05 04:37:46 PM PDT 24 | 350849133 ps | ||
| T36 | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1403083313 | Jul 05 04:37:38 PM PDT 24 | Jul 05 04:37:43 PM PDT 24 | 307983208 ps | ||
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| T61 | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1955630037 | Jul 05 04:37:49 PM PDT 24 | Jul 05 04:37:53 PM PDT 24 | 188309420 ps | ||
| T104 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1402591427 | Jul 05 04:37:39 PM PDT 24 | Jul 05 04:37:42 PM PDT 24 | 132719109 ps | ||
| T81 | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.47686961 | Jul 05 04:38:00 PM PDT 24 | Jul 05 04:38:08 PM PDT 24 | 818208375 ps | ||
| T105 | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2302830677 | Jul 05 04:37:42 PM PDT 24 | Jul 05 04:37:45 PM PDT 24 | 163604386 ps | ||
| T70 | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.676823651 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 130709070 ps | ||
| T106 | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.704453795 | Jul 05 04:37:37 PM PDT 24 | Jul 05 04:37:41 PM PDT 24 | 275455237 ps | ||
| T76 | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.622736825 | Jul 05 04:37:50 PM PDT 24 | Jul 05 04:37:52 PM PDT 24 | 61165349 ps | ||
| T73 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2505362294 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:52 PM PDT 24 | 936229039 ps | ||
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| T107 | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1462579400 | Jul 05 04:37:38 PM PDT 24 | Jul 05 04:37:41 PM PDT 24 | 332601805 ps | ||
| T108 | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4122433504 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 202079276 ps | ||
| T38 | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3059434276 | Jul 05 04:37:41 PM PDT 24 | Jul 05 04:37:44 PM PDT 24 | 194954940 ps | ||
| T109 | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3702747495 | Jul 05 04:37:51 PM PDT 24 | Jul 05 04:37:56 PM PDT 24 | 104333386 ps | ||
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| T111 | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1467021312 | Jul 05 04:37:38 PM PDT 24 | Jul 05 04:37:41 PM PDT 24 | 214520762 ps | ||
| T112 | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.827958866 | Jul 05 04:38:02 PM PDT 24 | Jul 05 04:38:07 PM PDT 24 | 55392697 ps | ||
| T113 | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2816509527 | Jul 05 04:37:37 PM PDT 24 | Jul 05 04:37:42 PM PDT 24 | 152725137 ps | ||
| T83 | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2170876648 | Jul 05 04:37:43 PM PDT 24 | Jul 05 04:37:49 PM PDT 24 | 1489835527 ps | ||
| T114 | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.297615399 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:47 PM PDT 24 | 59942008 ps | ||
| T82 | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3026604698 | Jul 05 04:37:47 PM PDT 24 | Jul 05 04:37:54 PM PDT 24 | 1730970871 ps | ||
| T115 | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2764973329 | Jul 05 04:37:30 PM PDT 24 | Jul 05 04:37:34 PM PDT 24 | 127802125 ps | ||
| T116 | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3319729921 | Jul 05 04:37:39 PM PDT 24 | Jul 05 04:37:41 PM PDT 24 | 105868498 ps | ||
| T117 | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1056541897 | Jul 05 04:37:50 PM PDT 24 | Jul 05 04:37:56 PM PDT 24 | 526511878 ps | ||
| T118 | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3783114408 | Jul 05 04:37:49 PM PDT 24 | Jul 05 04:37:51 PM PDT 24 | 29408707 ps | ||
| T119 | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2301554407 | Jul 05 04:37:48 PM PDT 24 | Jul 05 04:37:51 PM PDT 24 | 88399399 ps | ||
| T120 | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2594120173 | Jul 05 04:37:42 PM PDT 24 | Jul 05 04:37:46 PM PDT 24 | 264394633 ps | ||
| T39 | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2803991627 | Jul 05 04:37:47 PM PDT 24 | Jul 05 04:37:50 PM PDT 24 | 140637320 ps | ||
| T49 | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2755146118 | Jul 05 04:37:42 PM PDT 24 | Jul 05 04:37:45 PM PDT 24 | 197071600 ps | ||
| T50 | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1474570329 | Jul 05 04:37:36 PM PDT 24 | Jul 05 04:37:38 PM PDT 24 | 120323025 ps | ||
| T121 | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2560256651 | Jul 05 04:37:30 PM PDT 24 | Jul 05 04:37:36 PM PDT 24 | 304274934 ps | ||
| T122 | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3391482292 | Jul 05 04:37:49 PM PDT 24 | Jul 05 04:37:51 PM PDT 24 | 77092698 ps | ||
| T123 | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3087494445 | Jul 05 04:37:43 PM PDT 24 | Jul 05 04:37:46 PM PDT 24 | 107233609 ps | ||
| T55 | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3196219759 | Jul 05 04:37:38 PM PDT 24 | Jul 05 04:37:40 PM PDT 24 | 45627960 ps | ||
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| T88 | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1737273295 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:49 PM PDT 24 | 406774117 ps | ||
| T85 | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.509828836 | Jul 05 04:37:52 PM PDT 24 | Jul 05 04:37:57 PM PDT 24 | 528174606 ps | ||
| T125 | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.62506528 | Jul 05 04:38:05 PM PDT 24 | Jul 05 04:38:11 PM PDT 24 | 105885309 ps | ||
| T126 | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3871901568 | Jul 05 04:37:57 PM PDT 24 | Jul 05 04:38:01 PM PDT 24 | 127838868 ps | ||
| T127 | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1420216221 | Jul 05 04:37:56 PM PDT 24 | Jul 05 04:38:00 PM PDT 24 | 47938127 ps | ||
| T128 | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2758233856 | Jul 05 04:37:45 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 51625041 ps | ||
| T129 | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2407341465 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:47 PM PDT 24 | 35002137 ps | ||
| T130 | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2390247311 | Jul 05 04:37:35 PM PDT 24 | Jul 05 04:37:37 PM PDT 24 | 90436528 ps | ||
| T131 | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3816801525 | Jul 05 04:37:38 PM PDT 24 | Jul 05 04:37:44 PM PDT 24 | 743961247 ps | ||
| T86 | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1931900470 | Jul 05 04:37:47 PM PDT 24 | Jul 05 04:37:54 PM PDT 24 | 584365494 ps | ||
| T51 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1135533451 | Jul 05 04:37:47 PM PDT 24 | Jul 05 04:37:58 PM PDT 24 | 1881494473 ps | ||
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| T52 | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3938774373 | Jul 05 04:37:55 PM PDT 24 | Jul 05 04:37:58 PM PDT 24 | 48342424 ps | ||
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| T134 | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3310607262 | Jul 05 04:37:49 PM PDT 24 | Jul 05 04:37:53 PM PDT 24 | 123388246 ps | ||
| T135 | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3616798699 | Jul 05 04:37:50 PM PDT 24 | Jul 05 04:37:53 PM PDT 24 | 109634827 ps | ||
| T53 | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4016022906 | Jul 05 04:37:59 PM PDT 24 | Jul 05 04:38:12 PM PDT 24 | 1562294489 ps | ||
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| T140 | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2304395751 | Jul 05 04:37:39 PM PDT 24 | Jul 05 04:37:41 PM PDT 24 | 149969693 ps | ||
| T141 | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2413252695 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 61659522 ps | ||
| T142 | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1493649607 | Jul 05 04:37:58 PM PDT 24 | Jul 05 04:38:03 PM PDT 24 | 167283859 ps | ||
| T64 | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4124530498 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:51 PM PDT 24 | 804557500 ps | ||
| T143 | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2286346547 | Jul 05 04:37:55 PM PDT 24 | Jul 05 04:37:57 PM PDT 24 | 39983180 ps | ||
| T58 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1230196560 | Jul 05 04:37:30 PM PDT 24 | Jul 05 04:37:34 PM PDT 24 | 69797115 ps | ||
| T54 | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1926684585 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:49 PM PDT 24 | 114722283 ps | ||
| T144 | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2244184791 | Jul 05 04:38:01 PM PDT 24 | Jul 05 04:38:05 PM PDT 24 | 48298847 ps | ||
| T145 | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3047924250 | Jul 05 04:38:00 PM PDT 24 | Jul 05 04:38:04 PM PDT 24 | 38972505 ps | ||
| T146 | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1253856767 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:50 PM PDT 24 | 688963033 ps | ||
| T10 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3328022048 | Jul 05 04:37:42 PM PDT 24 | Jul 05 04:37:44 PM PDT 24 | 114776340 ps | ||
| T147 | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.680697688 | Jul 05 04:38:07 PM PDT 24 | Jul 05 04:38:12 PM PDT 24 | 51793334 ps | ||
| T148 | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1239412719 | Jul 05 04:37:51 PM PDT 24 | Jul 05 04:37:55 PM PDT 24 | 178595899 ps | ||
| T149 | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3436346640 | Jul 05 04:37:45 PM PDT 24 | Jul 05 04:37:50 PM PDT 24 | 177873222 ps | ||
| T150 | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.679121468 | Jul 05 04:37:51 PM PDT 24 | Jul 05 04:37:55 PM PDT 24 | 167571153 ps | ||
| T151 | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3576483282 | Jul 05 04:38:01 PM PDT 24 | Jul 05 04:38:05 PM PDT 24 | 40030675 ps | ||
| T152 | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1233366839 | Jul 05 04:38:00 PM PDT 24 | Jul 05 04:38:08 PM PDT 24 | 901435208 ps | ||
| T153 | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2296047275 | Jul 05 04:37:25 PM PDT 24 | Jul 05 04:37:34 PM PDT 24 | 296631362 ps | ||
| T154 | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2317571737 | Jul 05 04:37:46 PM PDT 24 | Jul 05 04:37:49 PM PDT 24 | 112732358 ps | ||
| T155 | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1796577757 | Jul 05 04:37:38 PM PDT 24 | Jul 05 04:37:41 PM PDT 24 | 258046148 ps | ||
| T156 | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2703822335 | Jul 05 04:37:52 PM PDT 24 | Jul 05 04:37:56 PM PDT 24 | 161644427 ps | ||
| T157 | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4087829227 | Jul 05 04:37:59 PM PDT 24 | Jul 05 04:38:03 PM PDT 24 | 72889967 ps | ||
| T87 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1463173473 | Jul 05 04:37:45 PM PDT 24 | Jul 05 04:37:50 PM PDT 24 | 564633273 ps | ||
| T59 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.184521023 | Jul 05 04:37:45 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 124977816 ps | ||
| T158 | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1668248294 | Jul 05 04:38:07 PM PDT 24 | Jul 05 04:38:12 PM PDT 24 | 46707156 ps | ||
| T159 | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3150766890 | Jul 05 04:38:01 PM PDT 24 | Jul 05 04:38:05 PM PDT 24 | 41892890 ps | ||
| T160 | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.342777846 | Jul 05 04:37:56 PM PDT 24 | Jul 05 04:38:00 PM PDT 24 | 84140170 ps | ||
| T161 | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3947646322 | Jul 05 04:37:45 PM PDT 24 | Jul 05 04:37:48 PM PDT 24 | 146674439 ps | ||
| T162 | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3085246279 | Jul 05 04:37:43 PM PDT 24 | Jul 05 04:37:46 PM PDT 24 | 82093047 ps | ||
| T163 | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3620278417 | Jul 05 04:37:56 PM PDT 24 | Jul 05 04:37:59 PM PDT 24 | 37352226 ps | ||
| T164 | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.431102401 | Jul 05 04:37:48 PM PDT 24 | Jul 05 04:37:50 PM PDT 24 | 116815502 ps | ||
| T165 | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1357325273 | Jul 05 04:37:43 PM PDT 24 | Jul 05 04:37:47 PM PDT 24 | 513804408 ps | ||
| T166 | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.976172351 | Jul 05 04:37:48 PM PDT 24 | Jul 05 04:37:51 PM PDT 24 | 153829173 ps | ||
| T167 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.368186719 | Jul 05 04:38:04 PM PDT 24 | Jul 05 04:38:12 PM PDT 24 | 693324856 ps | ||
| T12 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1970464000 | Jul 05 04:37:36 PM PDT 24 | Jul 05 04:37:38 PM PDT 24 | 73008911 ps | ||
| T168 | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3788041939 | Jul 05 04:37:42 PM PDT 24 | Jul 05 04:37:45 PM PDT 24 | 198062028 ps | ||
| T169 | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1815108629 | Jul 05 04:37:47 PM PDT 24 | Jul 05 04:37:53 PM PDT 24 | 496020924 ps | ||
| T170 | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3680328044 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:47 PM PDT 24 | 50946413 ps | ||
| T171 | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3337750518 | Jul 05 04:37:44 PM PDT 24 | Jul 05 04:37:47 PM PDT 24 | 46311786 ps | ||
| T172 | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1498515579 | Jul 05 04:37:52 PM PDT 24 | Jul 05 04:37:55 PM PDT 24 | 60494303 ps | ||
| T173 | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2627779382 | Jul 05 04:37:58 PM PDT 24 | Jul 05 04:38:01 PM PDT 24 | 64055228 ps | ||
| T174 | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3276606084 | Jul 05 04:37:55 PM PDT 24 | Jul 05 04:37:58 PM PDT 24 | 74278010 ps | ||
| T175 | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2266688962 | Jul 05 04:37:54 PM PDT 24 | Jul 05 04:37:57 PM PDT 24 | 59757298 ps |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.704622342 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1666720957 ps |
| CPU time | 5.76 seconds |
| Started | Jul 05 04:37:37 PM PDT 24 |
| Finished | Jul 05 04:37:43 PM PDT 24 |
| Peak memory | 205976 kb |
| Host | smart-85cfd8cb-46da-4d85-94d4-9234d62d3f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=704622342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.704622342 |
| Directory | /workspace/5.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1569926655 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 79487944 ps |
| CPU time | 0.74 seconds |
| Started | Jul 05 04:37:50 PM PDT 24 |
| Finished | Jul 05 04:37:53 PM PDT 24 |
| Peak memory | 205732 kb |
| Host | smart-26a87c9a-7c44-4523-98fe-f8137c0e9f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1569926655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1569926655 |
| Directory | /workspace/18.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.825382509 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 130520260 ps |
| CPU time | 0.95 seconds |
| Started | Jul 05 04:37:48 PM PDT 24 |
| Finished | Jul 05 04:37:51 PM PDT 24 |
| Peak memory | 205712 kb |
| Host | smart-eb09e2dc-f6e8-4007-ad68-9b0b8ae67a46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=825382509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.825382509 |
| Directory | /workspace/1.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2390322916 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 181419441 ps |
| CPU time | 1.66 seconds |
| Started | Jul 05 04:37:55 PM PDT 24 |
| Finished | Jul 05 04:37:59 PM PDT 24 |
| Peak memory | 214280 kb |
| Host | smart-030ffc87-71b2-47a4-b590-c64e632e78cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390322916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde v_csr_mem_rw_with_rand_reset.2390322916 |
| Directory | /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2836933703 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 30907455 ps |
| CPU time | 0.64 seconds |
| Started | Jul 05 04:37:45 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 205728 kb |
| Host | smart-a6651723-cbcc-4cbc-9527-1ad85ec6b769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2836933703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2836933703 |
| Directory | /workspace/6.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4136565993 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 55736104 ps |
| CPU time | 0.72 seconds |
| Started | Jul 05 04:38:02 PM PDT 24 |
| Finished | Jul 05 04:38:06 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-4dfa095a-40db-4e2f-a400-c8cb9fdd5b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4136565993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.4136565993 |
| Directory | /workspace/47.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.941532584 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 269568494 ps |
| CPU time | 3.33 seconds |
| Started | Jul 05 04:37:55 PM PDT 24 |
| Finished | Jul 05 04:38:01 PM PDT 24 |
| Peak memory | 221972 kb |
| Host | smart-651941ec-e635-4c6c-a907-d685373c6d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=941532584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.941532584 |
| Directory | /workspace/17.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3328022048 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 114776340 ps |
| CPU time | 0.93 seconds |
| Started | Jul 05 04:37:42 PM PDT 24 |
| Finished | Jul 05 04:37:44 PM PDT 24 |
| Peak memory | 205820 kb |
| Host | smart-438a7280-a40e-4e04-9dbd-826cc4bfd0c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3328022048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3328022048 |
| Directory | /workspace/0.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2505362294 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 936229039 ps |
| CPU time | 5.21 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:52 PM PDT 24 |
| Peak memory | 205980 kb |
| Host | smart-34be8a3c-1fb3-4e0c-8a87-436a8a64f393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2505362294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2505362294 |
| Directory | /workspace/6.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.983528976 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 50355482 ps |
| CPU time | 0.74 seconds |
| Started | Jul 05 04:38:01 PM PDT 24 |
| Finished | Jul 05 04:38:06 PM PDT 24 |
| Peak memory | 205672 kb |
| Host | smart-15017f4a-1d31-4a27-8d19-ec13c2330053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=983528976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.983528976 |
| Directory | /workspace/37.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.639964256 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 227136412 ps |
| CPU time | 1.89 seconds |
| Started | Jul 05 04:37:39 PM PDT 24 |
| Finished | Jul 05 04:37:42 PM PDT 24 |
| Peak memory | 205908 kb |
| Host | smart-9151bcdf-0443-4a3f-bf12-2a9d39b5897a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=639964256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.639964256 |
| Directory | /workspace/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.761135901 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 51838981 ps |
| CPU time | 0.69 seconds |
| Started | Jul 05 04:37:51 PM PDT 24 |
| Finished | Jul 05 04:37:54 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-f6efb28c-4be0-4c39-95d3-e1185ac2fe20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=761135901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.761135901 |
| Directory | /workspace/14.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4287981532 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 44130989 ps |
| CPU time | 0.69 seconds |
| Started | Jul 05 04:37:39 PM PDT 24 |
| Finished | Jul 05 04:37:41 PM PDT 24 |
| Peak memory | 205728 kb |
| Host | smart-33823634-01bb-4912-a328-aa9604ae6f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4287981532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.4287981532 |
| Directory | /workspace/1.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1233366839 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 901435208 ps |
| CPU time | 4.6 seconds |
| Started | Jul 05 04:38:00 PM PDT 24 |
| Finished | Jul 05 04:38:08 PM PDT 24 |
| Peak memory | 205928 kb |
| Host | smart-f8653933-fc61-45fa-a62a-363619fc43ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1233366839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1233366839 |
| Directory | /workspace/12.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4016022906 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1562294489 ps |
| CPU time | 9.49 seconds |
| Started | Jul 05 04:37:59 PM PDT 24 |
| Finished | Jul 05 04:38:12 PM PDT 24 |
| Peak memory | 205956 kb |
| Host | smart-e8413fba-da9d-4de2-bc3e-f4a97f8c1945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4016022906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.4016022906 |
| Directory | /workspace/0.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4223956150 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 742668192 ps |
| CPU time | 4.43 seconds |
| Started | Jul 05 04:37:53 PM PDT 24 |
| Finished | Jul 05 04:37:59 PM PDT 24 |
| Peak memory | 205872 kb |
| Host | smart-26fd9674-9526-4819-80b0-e50e581a9e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4223956150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.4223956150 |
| Directory | /workspace/3.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.509828836 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 528174606 ps |
| CPU time | 3.08 seconds |
| Started | Jul 05 04:37:52 PM PDT 24 |
| Finished | Jul 05 04:37:57 PM PDT 24 |
| Peak memory | 205960 kb |
| Host | smart-8f8f225d-e250-4d1c-b0a5-70aedca385e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=509828836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.509828836 |
| Directory | /workspace/1.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4294070866 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 124470375 ps |
| CPU time | 3.44 seconds |
| Started | Jul 05 04:37:47 PM PDT 24 |
| Finished | Jul 05 04:37:53 PM PDT 24 |
| Peak memory | 221792 kb |
| Host | smart-4d2354e6-2e0c-46eb-897b-0df92c51c1d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4294070866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.4294070866 |
| Directory | /workspace/1.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4124530498 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 804557500 ps |
| CPU time | 4.79 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:51 PM PDT 24 |
| Peak memory | 205972 kb |
| Host | smart-f1692b02-20c3-47c2-ac8f-866418f1350f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4124530498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.4124530498 |
| Directory | /workspace/19.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2296047275 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 296631362 ps |
| CPU time | 3.44 seconds |
| Started | Jul 05 04:37:25 PM PDT 24 |
| Finished | Jul 05 04:37:34 PM PDT 24 |
| Peak memory | 206008 kb |
| Host | smart-3cbb4935-3952-4408-a987-2261db0ab219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2296047275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2296047275 |
| Directory | /workspace/0.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2764973329 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 127802125 ps |
| CPU time | 1.29 seconds |
| Started | Jul 05 04:37:30 PM PDT 24 |
| Finished | Jul 05 04:37:34 PM PDT 24 |
| Peak memory | 214148 kb |
| Host | smart-c5ea7ee1-5f45-41ab-9860-fcea1e11506a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764973329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde v_csr_mem_rw_with_rand_reset.2764973329 |
| Directory | /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.906316804 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 84434996 ps |
| CPU time | 1.07 seconds |
| Started | Jul 05 04:37:24 PM PDT 24 |
| Finished | Jul 05 04:37:31 PM PDT 24 |
| Peak memory | 205872 kb |
| Host | smart-6f243c66-9eae-4678-945e-25711f9d08e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=906316804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.906316804 |
| Directory | /workspace/0.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3783114408 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 29408707 ps |
| CPU time | 0.63 seconds |
| Started | Jul 05 04:37:49 PM PDT 24 |
| Finished | Jul 05 04:37:51 PM PDT 24 |
| Peak memory | 205732 kb |
| Host | smart-d278be58-3e71-47ce-8ee5-d0be88f5d87e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3783114408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3783114408 |
| Directory | /workspace/0.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2803991627 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 140637320 ps |
| CPU time | 1.47 seconds |
| Started | Jul 05 04:37:47 PM PDT 24 |
| Finished | Jul 05 04:37:50 PM PDT 24 |
| Peak memory | 214140 kb |
| Host | smart-7fdc127b-211c-4dce-ae53-59e9a5641b82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2803991627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2803991627 |
| Directory | /workspace/0.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1796577757 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 258046148 ps |
| CPU time | 2.43 seconds |
| Started | Jul 05 04:37:38 PM PDT 24 |
| Finished | Jul 05 04:37:41 PM PDT 24 |
| Peak memory | 205936 kb |
| Host | smart-193fb325-d5a3-4b98-ba52-6dec976767c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1796577757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1796577757 |
| Directory | /workspace/0.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2545465183 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 114331907 ps |
| CPU time | 1.49 seconds |
| Started | Jul 05 04:37:39 PM PDT 24 |
| Finished | Jul 05 04:37:42 PM PDT 24 |
| Peak memory | 205912 kb |
| Host | smart-2c7d276b-8c1d-4a1a-a215-619bcb913b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2545465183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2545465183 |
| Directory | /workspace/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1402591427 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 132719109 ps |
| CPU time | 1.68 seconds |
| Started | Jul 05 04:37:39 PM PDT 24 |
| Finished | Jul 05 04:37:42 PM PDT 24 |
| Peak memory | 205992 kb |
| Host | smart-69e5a82f-e591-4099-98a8-165752ef3865 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1402591427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1402591427 |
| Directory | /workspace/0.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1056541897 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 526511878 ps |
| CPU time | 3.82 seconds |
| Started | Jul 05 04:37:50 PM PDT 24 |
| Finished | Jul 05 04:37:56 PM PDT 24 |
| Peak memory | 205932 kb |
| Host | smart-4e557e84-3849-447a-ada3-af22fe2bce47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1056541897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1056541897 |
| Directory | /workspace/0.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1926684585 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 114722283 ps |
| CPU time | 3.18 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:49 PM PDT 24 |
| Peak memory | 205928 kb |
| Host | smart-5ce608b9-e502-495c-a478-9a1914a27fb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1926684585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1926684585 |
| Directory | /workspace/1.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1135533451 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1881494473 ps |
| CPU time | 8.94 seconds |
| Started | Jul 05 04:37:47 PM PDT 24 |
| Finished | Jul 05 04:37:58 PM PDT 24 |
| Peak memory | 205944 kb |
| Host | smart-0ff3ffe7-bdf7-4f06-b20f-8b001f94333a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1135533451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1135533451 |
| Directory | /workspace/1.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1733785233 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 111811113 ps |
| CPU time | 1.27 seconds |
| Started | Jul 05 04:37:30 PM PDT 24 |
| Finished | Jul 05 04:37:34 PM PDT 24 |
| Peak memory | 214156 kb |
| Host | smart-3be6e8b2-b04c-47b2-84c0-13ec052b129b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733785233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde v_csr_mem_rw_with_rand_reset.1733785233 |
| Directory | /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1896344851 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 157515518 ps |
| CPU time | 1.14 seconds |
| Started | Jul 05 04:37:53 PM PDT 24 |
| Finished | Jul 05 04:37:56 PM PDT 24 |
| Peak memory | 205904 kb |
| Host | smart-51f96fde-bd7d-4dd4-a61b-b35bbec75ba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1896344851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1896344851 |
| Directory | /workspace/1.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1474570329 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 120323025 ps |
| CPU time | 1.5 seconds |
| Started | Jul 05 04:37:36 PM PDT 24 |
| Finished | Jul 05 04:37:38 PM PDT 24 |
| Peak memory | 214204 kb |
| Host | smart-05d897c5-a2cf-44de-afe3-9c55f53534c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1474570329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1474570329 |
| Directory | /workspace/1.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1129760976 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 111671303 ps |
| CPU time | 2.35 seconds |
| Started | Jul 05 04:37:39 PM PDT 24 |
| Finished | Jul 05 04:37:43 PM PDT 24 |
| Peak memory | 206160 kb |
| Host | smart-79c8cf5c-a921-4a90-86ae-5a0fcc8330c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1129760976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1129760976 |
| Directory | /workspace/1.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.62506528 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 105885309 ps |
| CPU time | 2.12 seconds |
| Started | Jul 05 04:38:05 PM PDT 24 |
| Finished | Jul 05 04:38:11 PM PDT 24 |
| Peak memory | 214172 kb |
| Host | smart-8b0039eb-c246-45e2-9eed-c57ac4882f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62506528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev _csr_mem_rw_with_rand_reset.62506528 |
| Directory | /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2758233856 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 51625041 ps |
| CPU time | 0.78 seconds |
| Started | Jul 05 04:37:45 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-f6f8118d-4455-47aa-a06f-881a939ef096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2758233856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2758233856 |
| Directory | /workspace/10.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1605152938 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 69449315 ps |
| CPU time | 0.7 seconds |
| Started | Jul 05 04:37:41 PM PDT 24 |
| Finished | Jul 05 04:37:43 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-b8700a6f-6ad2-4fc6-bb53-c87d45c295ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1605152938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1605152938 |
| Directory | /workspace/10.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3087494445 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 107233609 ps |
| CPU time | 1.5 seconds |
| Started | Jul 05 04:37:43 PM PDT 24 |
| Finished | Jul 05 04:37:46 PM PDT 24 |
| Peak memory | 205996 kb |
| Host | smart-41024937-ca7f-4dbd-a1ef-c1f4ee0a52bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3087494445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3087494445 |
| Directory | /workspace/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2594120173 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 264394633 ps |
| CPU time | 2.68 seconds |
| Started | Jul 05 04:37:42 PM PDT 24 |
| Finished | Jul 05 04:37:46 PM PDT 24 |
| Peak memory | 214224 kb |
| Host | smart-e4436c07-7c25-4277-9349-beba8466dc0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2594120173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2594120173 |
| Directory | /workspace/10.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1815108629 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 496020924 ps |
| CPU time | 4.4 seconds |
| Started | Jul 05 04:37:47 PM PDT 24 |
| Finished | Jul 05 04:37:53 PM PDT 24 |
| Peak memory | 205964 kb |
| Host | smart-c03093fe-9bbc-46f5-8478-a3b77642412f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1815108629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1815108629 |
| Directory | /workspace/10.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2301554407 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 88399399 ps |
| CPU time | 1.26 seconds |
| Started | Jul 05 04:37:48 PM PDT 24 |
| Finished | Jul 05 04:37:51 PM PDT 24 |
| Peak memory | 214232 kb |
| Host | smart-34f0c774-0947-4746-adc7-c72eb29d3b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301554407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.2301554407 |
| Directory | /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.162249845 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 80138880 ps |
| CPU time | 1.05 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 205968 kb |
| Host | smart-0d8ada74-9f5e-4e22-b80a-c5f145ed0379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=162249845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.162249845 |
| Directory | /workspace/11.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3337750518 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 46311786 ps |
| CPU time | 0.67 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:47 PM PDT 24 |
| Peak memory | 205804 kb |
| Host | smart-bfa54311-8a0f-4b37-9cc7-5c36c588ed50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3337750518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3337750518 |
| Directory | /workspace/11.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2927598535 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 109696764 ps |
| CPU time | 1.58 seconds |
| Started | Jul 05 04:37:52 PM PDT 24 |
| Finished | Jul 05 04:37:56 PM PDT 24 |
| Peak memory | 205988 kb |
| Host | smart-bc5ca94d-e023-445b-baec-73329d2fa41a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2927598535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2927598535 |
| Directory | /workspace/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3788041939 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 198062028 ps |
| CPU time | 2.24 seconds |
| Started | Jul 05 04:37:42 PM PDT 24 |
| Finished | Jul 05 04:37:45 PM PDT 24 |
| Peak memory | 214224 kb |
| Host | smart-08f3c333-7bd9-48af-82b2-946205d34943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3788041939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3788041939 |
| Directory | /workspace/11.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1463173473 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 564633273 ps |
| CPU time | 2.93 seconds |
| Started | Jul 05 04:37:45 PM PDT 24 |
| Finished | Jul 05 04:37:50 PM PDT 24 |
| Peak memory | 205916 kb |
| Host | smart-aaa677ee-11d5-4b11-a53a-1302fa6f0dff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1463173473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1463173473 |
| Directory | /workspace/11.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.574293990 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 55251607 ps |
| CPU time | 1.18 seconds |
| Started | Jul 05 04:37:56 PM PDT 24 |
| Finished | Jul 05 04:37:59 PM PDT 24 |
| Peak memory | 214288 kb |
| Host | smart-83523a58-3379-4154-88de-685095803565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574293990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde v_csr_mem_rw_with_rand_reset.574293990 |
| Directory | /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3680328044 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 50946413 ps |
| CPU time | 0.79 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:47 PM PDT 24 |
| Peak memory | 205804 kb |
| Host | smart-84c68f31-653f-405a-b83b-b90b4ed90241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3680328044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3680328044 |
| Directory | /workspace/12.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2619797196 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 48005733 ps |
| CPU time | 0.66 seconds |
| Started | Jul 05 04:38:04 PM PDT 24 |
| Finished | Jul 05 04:38:08 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-d1148fda-3f83-4421-9fb0-20427e54ee5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2619797196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2619797196 |
| Directory | /workspace/12.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.188280878 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 200210205 ps |
| CPU time | 1.59 seconds |
| Started | Jul 05 04:37:50 PM PDT 24 |
| Finished | Jul 05 04:37:54 PM PDT 24 |
| Peak memory | 205920 kb |
| Host | smart-f45aaef6-1ad4-4515-895a-3f94778fec76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=188280878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.188280878 |
| Directory | /workspace/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3849450467 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 85520520 ps |
| CPU time | 1.99 seconds |
| Started | Jul 05 04:37:56 PM PDT 24 |
| Finished | Jul 05 04:38:00 PM PDT 24 |
| Peak memory | 214176 kb |
| Host | smart-1355ba91-327d-49c9-87e9-d9f5b707608d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3849450467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3849450467 |
| Directory | /workspace/12.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2307446807 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 108169628 ps |
| CPU time | 1.28 seconds |
| Started | Jul 05 04:37:52 PM PDT 24 |
| Finished | Jul 05 04:37:56 PM PDT 24 |
| Peak memory | 214220 kb |
| Host | smart-8880ad77-6ac1-48c8-9de7-d025022fb623 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307446807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.2307446807 |
| Directory | /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3391482292 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 77092698 ps |
| CPU time | 0.87 seconds |
| Started | Jul 05 04:37:49 PM PDT 24 |
| Finished | Jul 05 04:37:51 PM PDT 24 |
| Peak memory | 205728 kb |
| Host | smart-bed60d27-d78a-4e47-aa5a-7a96ecbe23dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3391482292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3391482292 |
| Directory | /workspace/13.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2266688962 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 59757298 ps |
| CPU time | 0.7 seconds |
| Started | Jul 05 04:37:54 PM PDT 24 |
| Finished | Jul 05 04:37:57 PM PDT 24 |
| Peak memory | 205768 kb |
| Host | smart-83afe51a-9c60-459d-ac0e-5bf807914b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2266688962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2266688962 |
| Directory | /workspace/13.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3054103663 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 93795715 ps |
| CPU time | 1.08 seconds |
| Started | Jul 05 04:37:54 PM PDT 24 |
| Finished | Jul 05 04:37:57 PM PDT 24 |
| Peak memory | 206020 kb |
| Host | smart-193683de-7cd5-4520-8504-cbe7388ca5ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3054103663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3054103663 |
| Directory | /workspace/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3865973234 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 216348389 ps |
| CPU time | 2.2 seconds |
| Started | Jul 05 04:37:55 PM PDT 24 |
| Finished | Jul 05 04:37:59 PM PDT 24 |
| Peak memory | 214288 kb |
| Host | smart-3bbe0c30-d436-43bf-8f93-1419d4143bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3865973234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3865973234 |
| Directory | /workspace/13.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1737273295 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 406774117 ps |
| CPU time | 2.67 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:49 PM PDT 24 |
| Peak memory | 205916 kb |
| Host | smart-125c04b8-2494-4d96-afff-0e82c56cdc73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1737273295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1737273295 |
| Directory | /workspace/13.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.954907930 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 126078708 ps |
| CPU time | 1.35 seconds |
| Started | Jul 05 04:38:02 PM PDT 24 |
| Finished | Jul 05 04:38:08 PM PDT 24 |
| Peak memory | 215884 kb |
| Host | smart-f1f0852a-18a9-4745-aab1-988cfd63f333 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954907930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde v_csr_mem_rw_with_rand_reset.954907930 |
| Directory | /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4255441661 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 123248770 ps |
| CPU time | 1.05 seconds |
| Started | Jul 05 04:37:49 PM PDT 24 |
| Finished | Jul 05 04:37:52 PM PDT 24 |
| Peak memory | 205940 kb |
| Host | smart-a7880363-3cbd-4fd7-b3e6-7ba4f11e7d13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4255441661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4255441661 |
| Directory | /workspace/14.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.600837467 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 135251951 ps |
| CPU time | 1.23 seconds |
| Started | Jul 05 04:38:03 PM PDT 24 |
| Finished | Jul 05 04:38:09 PM PDT 24 |
| Peak memory | 205880 kb |
| Host | smart-e551fc5b-1c10-438d-9b29-82bca968c756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=600837467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.600837467 |
| Directory | /workspace/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3310607262 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 123388246 ps |
| CPU time | 2.06 seconds |
| Started | Jul 05 04:37:49 PM PDT 24 |
| Finished | Jul 05 04:37:53 PM PDT 24 |
| Peak memory | 221648 kb |
| Host | smart-76f6713a-7bf3-473b-89e5-af886cf9aeb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3310607262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3310607262 |
| Directory | /workspace/14.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.894647842 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 431725657 ps |
| CPU time | 2.81 seconds |
| Started | Jul 05 04:37:43 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 205960 kb |
| Host | smart-3d971bb7-d568-4111-8709-692b156929d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=894647842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.894647842 |
| Directory | /workspace/14.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1793846955 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 102144007 ps |
| CPU time | 2.37 seconds |
| Started | Jul 05 04:37:45 PM PDT 24 |
| Finished | Jul 05 04:37:50 PM PDT 24 |
| Peak memory | 214104 kb |
| Host | smart-c55ee289-b582-4e86-a329-d0feda3b66ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793846955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd ev_csr_mem_rw_with_rand_reset.1793846955 |
| Directory | /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1668248294 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 46707156 ps |
| CPU time | 0.92 seconds |
| Started | Jul 05 04:38:07 PM PDT 24 |
| Finished | Jul 05 04:38:12 PM PDT 24 |
| Peak memory | 205960 kb |
| Host | smart-c31b7f40-488b-4664-b1ae-252559d2cfe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1668248294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1668248294 |
| Directory | /workspace/15.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1499010237 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 54247011 ps |
| CPU time | 0.71 seconds |
| Started | Jul 05 04:38:02 PM PDT 24 |
| Finished | Jul 05 04:38:07 PM PDT 24 |
| Peak memory | 205776 kb |
| Host | smart-1a00aaad-fae5-4ba8-86fa-d016c5635b72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1499010237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1499010237 |
| Directory | /workspace/15.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1856678158 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 174345530 ps |
| CPU time | 1.32 seconds |
| Started | Jul 05 04:38:02 PM PDT 24 |
| Finished | Jul 05 04:38:08 PM PDT 24 |
| Peak memory | 205980 kb |
| Host | smart-3256cead-9238-4a0a-aa60-a45206ef40ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1856678158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1856678158 |
| Directory | /workspace/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1522074175 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 322465246 ps |
| CPU time | 3.29 seconds |
| Started | Jul 05 04:37:46 PM PDT 24 |
| Finished | Jul 05 04:37:52 PM PDT 24 |
| Peak memory | 214284 kb |
| Host | smart-3b5b275f-16cb-460c-babb-b0e9ec5728d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1522074175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1522074175 |
| Directory | /workspace/15.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1357325273 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 513804408 ps |
| CPU time | 2.66 seconds |
| Started | Jul 05 04:37:43 PM PDT 24 |
| Finished | Jul 05 04:37:47 PM PDT 24 |
| Peak memory | 206024 kb |
| Host | smart-5390044b-e63a-44e9-b90e-28144a42a274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1357325273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1357325273 |
| Directory | /workspace/15.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.514668303 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 89934056 ps |
| CPU time | 1.3 seconds |
| Started | Jul 05 04:37:56 PM PDT 24 |
| Finished | Jul 05 04:37:59 PM PDT 24 |
| Peak memory | 214204 kb |
| Host | smart-d61799b5-c56a-4103-80c4-5f8ca97ed75d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514668303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde v_csr_mem_rw_with_rand_reset.514668303 |
| Directory | /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.419781628 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 106354488 ps |
| CPU time | 0.92 seconds |
| Started | Jul 05 04:37:52 PM PDT 24 |
| Finished | Jul 05 04:37:55 PM PDT 24 |
| Peak memory | 205716 kb |
| Host | smart-0d69ceeb-40e7-4811-857a-9fed18ce409b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=419781628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.419781628 |
| Directory | /workspace/16.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1760180180 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 48726550 ps |
| CPU time | 0.67 seconds |
| Started | Jul 05 04:38:01 PM PDT 24 |
| Finished | Jul 05 04:38:05 PM PDT 24 |
| Peak memory | 205728 kb |
| Host | smart-4de56c99-b06b-4cb4-bcfb-0ca544c5ca5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1760180180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1760180180 |
| Directory | /workspace/16.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1493649607 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 167283859 ps |
| CPU time | 1.67 seconds |
| Started | Jul 05 04:37:58 PM PDT 24 |
| Finished | Jul 05 04:38:03 PM PDT 24 |
| Peak memory | 206012 kb |
| Host | smart-590f99c1-bac1-4778-be97-38f016acb238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1493649607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1493649607 |
| Directory | /workspace/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3436346640 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 177873222 ps |
| CPU time | 2.1 seconds |
| Started | Jul 05 04:37:45 PM PDT 24 |
| Finished | Jul 05 04:37:50 PM PDT 24 |
| Peak memory | 221592 kb |
| Host | smart-3161c29c-c705-41e8-a547-54281901f752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3436346640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3436346640 |
| Directory | /workspace/16.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3026604698 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1730970871 ps |
| CPU time | 5.22 seconds |
| Started | Jul 05 04:37:47 PM PDT 24 |
| Finished | Jul 05 04:37:54 PM PDT 24 |
| Peak memory | 205952 kb |
| Host | smart-c657d80f-b8d6-4108-a797-3a609d070af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3026604698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3026604698 |
| Directory | /workspace/16.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3059052051 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 162598162 ps |
| CPU time | 1.88 seconds |
| Started | Jul 05 04:37:48 PM PDT 24 |
| Finished | Jul 05 04:37:52 PM PDT 24 |
| Peak memory | 214168 kb |
| Host | smart-852a49af-f99b-44f8-bdab-74720ae7c871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059052051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.3059052051 |
| Directory | /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2703822335 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 161644427 ps |
| CPU time | 1.15 seconds |
| Started | Jul 05 04:37:52 PM PDT 24 |
| Finished | Jul 05 04:37:56 PM PDT 24 |
| Peak memory | 205968 kb |
| Host | smart-a1a17cb4-568a-4c47-83e4-709441923606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2703822335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2703822335 |
| Directory | /workspace/17.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3377612276 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 40746326 ps |
| CPU time | 0.7 seconds |
| Started | Jul 05 04:37:54 PM PDT 24 |
| Finished | Jul 05 04:37:56 PM PDT 24 |
| Peak memory | 205724 kb |
| Host | smart-2e1a19ef-757f-4ad8-911d-f432d6aa3f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3377612276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3377612276 |
| Directory | /workspace/17.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2363740525 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 95567327 ps |
| CPU time | 1.11 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 205964 kb |
| Host | smart-213088c2-7228-418d-a54d-130fc2077522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2363740525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2363740525 |
| Directory | /workspace/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.368186719 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 693324856 ps |
| CPU time | 4.47 seconds |
| Started | Jul 05 04:38:04 PM PDT 24 |
| Finished | Jul 05 04:38:12 PM PDT 24 |
| Peak memory | 205868 kb |
| Host | smart-7a774d22-1749-4f2a-9620-d004763447e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=368186719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.368186719 |
| Directory | /workspace/17.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2717136109 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 180309607 ps |
| CPU time | 1.91 seconds |
| Started | Jul 05 04:37:51 PM PDT 24 |
| Finished | Jul 05 04:37:55 PM PDT 24 |
| Peak memory | 214232 kb |
| Host | smart-d05b0443-614f-482f-9de6-7336a80453dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717136109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.2717136109 |
| Directory | /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1364540767 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 107860985 ps |
| CPU time | 0.91 seconds |
| Started | Jul 05 04:37:45 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 205772 kb |
| Host | smart-2952c748-5109-4461-8d86-0be44ee5b8d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1364540767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1364540767 |
| Directory | /workspace/18.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2381306197 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 97495935 ps |
| CPU time | 1.1 seconds |
| Started | Jul 05 04:38:06 PM PDT 24 |
| Finished | Jul 05 04:38:11 PM PDT 24 |
| Peak memory | 205996 kb |
| Host | smart-bd3910e7-f8d9-4c9c-8cd8-2bcd1b6d5651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2381306197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2381306197 |
| Directory | /workspace/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3702747495 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 104333386 ps |
| CPU time | 2.87 seconds |
| Started | Jul 05 04:37:51 PM PDT 24 |
| Finished | Jul 05 04:37:56 PM PDT 24 |
| Peak memory | 214200 kb |
| Host | smart-39df3902-fb26-4d47-ace3-bd404b7449ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3702747495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3702747495 |
| Directory | /workspace/18.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1931900470 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 584365494 ps |
| CPU time | 4.12 seconds |
| Started | Jul 05 04:37:47 PM PDT 24 |
| Finished | Jul 05 04:37:54 PM PDT 24 |
| Peak memory | 205952 kb |
| Host | smart-c5fd8266-b9ff-4ba6-bdee-a1bce1ec4de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1931900470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1931900470 |
| Directory | /workspace/18.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.679121468 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 167571153 ps |
| CPU time | 1.87 seconds |
| Started | Jul 05 04:37:51 PM PDT 24 |
| Finished | Jul 05 04:37:55 PM PDT 24 |
| Peak memory | 214236 kb |
| Host | smart-d22c9be1-fb38-4cc9-8400-19e3501c4a57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679121468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde v_csr_mem_rw_with_rand_reset.679121468 |
| Directory | /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3276606084 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 74278010 ps |
| CPU time | 0.85 seconds |
| Started | Jul 05 04:37:55 PM PDT 24 |
| Finished | Jul 05 04:37:58 PM PDT 24 |
| Peak memory | 205804 kb |
| Host | smart-623140d7-eb0d-416a-a9b7-3cfd147a4401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3276606084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3276606084 |
| Directory | /workspace/19.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.774902582 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 71605534 ps |
| CPU time | 0.73 seconds |
| Started | Jul 05 04:37:47 PM PDT 24 |
| Finished | Jul 05 04:37:50 PM PDT 24 |
| Peak memory | 205744 kb |
| Host | smart-a5e06c9e-a737-4787-afb0-7e15642b24bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=774902582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.774902582 |
| Directory | /workspace/19.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1239412719 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 178595899 ps |
| CPU time | 1.9 seconds |
| Started | Jul 05 04:37:51 PM PDT 24 |
| Finished | Jul 05 04:37:55 PM PDT 24 |
| Peak memory | 205968 kb |
| Host | smart-be58ac13-db58-4583-a861-70062c2fdb7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1239412719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1239412719 |
| Directory | /workspace/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2766736269 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 177145473 ps |
| CPU time | 2.34 seconds |
| Started | Jul 05 04:38:03 PM PDT 24 |
| Finished | Jul 05 04:38:10 PM PDT 24 |
| Peak memory | 214224 kb |
| Host | smart-1f7287fb-cdf2-4701-9b80-bc7db38d0660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2766736269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2766736269 |
| Directory | /workspace/19.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2848202252 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 191746529 ps |
| CPU time | 2.13 seconds |
| Started | Jul 05 04:37:56 PM PDT 24 |
| Finished | Jul 05 04:38:00 PM PDT 24 |
| Peak memory | 205892 kb |
| Host | smart-2154027c-6376-4425-b2e3-184eb7cb7115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2848202252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2848202252 |
| Directory | /workspace/2.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.204062099 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 370184923 ps |
| CPU time | 4.04 seconds |
| Started | Jul 05 04:37:52 PM PDT 24 |
| Finished | Jul 05 04:37:58 PM PDT 24 |
| Peak memory | 205880 kb |
| Host | smart-8964c1de-6579-40d0-9c50-85b6c106cd50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=204062099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.204062099 |
| Directory | /workspace/2.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.184521023 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 124977816 ps |
| CPU time | 0.86 seconds |
| Started | Jul 05 04:37:45 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-5d1343b2-6bef-4b2d-96cf-2d160706afe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=184521023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.184521023 |
| Directory | /workspace/2.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.676823651 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 130709070 ps |
| CPU time | 1.33 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 215984 kb |
| Host | smart-6d80bc1f-a49e-497c-b693-81d92bc11ffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676823651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev _csr_mem_rw_with_rand_reset.676823651 |
| Directory | /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3175699621 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 88130654 ps |
| CPU time | 0.97 seconds |
| Started | Jul 05 04:37:33 PM PDT 24 |
| Finished | Jul 05 04:37:35 PM PDT 24 |
| Peak memory | 205948 kb |
| Host | smart-b02d671f-56ed-4254-b7b7-a569788b7864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3175699621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3175699621 |
| Directory | /workspace/2.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1727851207 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 46585012 ps |
| CPU time | 0.69 seconds |
| Started | Jul 05 04:37:50 PM PDT 24 |
| Finished | Jul 05 04:37:53 PM PDT 24 |
| Peak memory | 205816 kb |
| Host | smart-71d37546-9e54-40a2-8d96-0ae0e11ed8cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1727851207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1727851207 |
| Directory | /workspace/2.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3059434276 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 194954940 ps |
| CPU time | 2.34 seconds |
| Started | Jul 05 04:37:41 PM PDT 24 |
| Finished | Jul 05 04:37:44 PM PDT 24 |
| Peak memory | 214144 kb |
| Host | smart-662e34b6-b510-4b23-986a-c6025dbeeae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3059434276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3059434276 |
| Directory | /workspace/2.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.704453795 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 275455237 ps |
| CPU time | 2.65 seconds |
| Started | Jul 05 04:37:37 PM PDT 24 |
| Finished | Jul 05 04:37:41 PM PDT 24 |
| Peak memory | 205904 kb |
| Host | smart-db686065-8578-4446-88b6-3a1a53134fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=704453795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.704453795 |
| Directory | /workspace/2.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1955630037 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 188309420 ps |
| CPU time | 1.54 seconds |
| Started | Jul 05 04:37:49 PM PDT 24 |
| Finished | Jul 05 04:37:53 PM PDT 24 |
| Peak memory | 205912 kb |
| Host | smart-4b6731d5-0802-4b8c-b771-7771e41634ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1955630037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1955630037 |
| Directory | /workspace/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2560256651 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 304274934 ps |
| CPU time | 3.18 seconds |
| Started | Jul 05 04:37:30 PM PDT 24 |
| Finished | Jul 05 04:37:36 PM PDT 24 |
| Peak memory | 214148 kb |
| Host | smart-fca1fa51-fccf-4f92-aafe-32269730602b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2560256651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2560256651 |
| Directory | /workspace/2.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.822987895 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 490764379 ps |
| CPU time | 2.43 seconds |
| Started | Jul 05 04:37:31 PM PDT 24 |
| Finished | Jul 05 04:37:36 PM PDT 24 |
| Peak memory | 205904 kb |
| Host | smart-dbced57a-d250-4634-b37a-718ca4a9af69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=822987895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.822987895 |
| Directory | /workspace/2.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.622736825 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 61165349 ps |
| CPU time | 0.69 seconds |
| Started | Jul 05 04:37:50 PM PDT 24 |
| Finished | Jul 05 04:37:52 PM PDT 24 |
| Peak memory | 205748 kb |
| Host | smart-dbc8da8e-7bec-4e23-bf68-11c5b10247b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=622736825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.622736825 |
| Directory | /workspace/20.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.761155409 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 47374147 ps |
| CPU time | 0.71 seconds |
| Started | Jul 05 04:37:52 PM PDT 24 |
| Finished | Jul 05 04:37:55 PM PDT 24 |
| Peak memory | 205804 kb |
| Host | smart-86a02cc5-e9f7-4e16-8a7d-1298eb78655b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=761155409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.761155409 |
| Directory | /workspace/21.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2951078646 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 35548940 ps |
| CPU time | 0.66 seconds |
| Started | Jul 05 04:37:51 PM PDT 24 |
| Finished | Jul 05 04:37:53 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-d27d0cff-3589-4988-bd54-2cdcdcc4ba30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2951078646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2951078646 |
| Directory | /workspace/22.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2627779382 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 64055228 ps |
| CPU time | 0.75 seconds |
| Started | Jul 05 04:37:58 PM PDT 24 |
| Finished | Jul 05 04:38:01 PM PDT 24 |
| Peak memory | 205756 kb |
| Host | smart-5d2dc6ab-18d7-4fb4-b3c2-1aa75bd5e3bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2627779382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2627779382 |
| Directory | /workspace/23.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3049820063 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 77304521 ps |
| CPU time | 0.72 seconds |
| Started | Jul 05 04:37:56 PM PDT 24 |
| Finished | Jul 05 04:37:59 PM PDT 24 |
| Peak memory | 205788 kb |
| Host | smart-edd80ae4-cbec-404a-a735-f4b263fa729d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3049820063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3049820063 |
| Directory | /workspace/24.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1498515579 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 60494303 ps |
| CPU time | 0.72 seconds |
| Started | Jul 05 04:37:52 PM PDT 24 |
| Finished | Jul 05 04:37:55 PM PDT 24 |
| Peak memory | 205796 kb |
| Host | smart-60ec6a70-39fb-40e0-8093-c30324954a9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1498515579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1498515579 |
| Directory | /workspace/25.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4087829227 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 72889967 ps |
| CPU time | 0.67 seconds |
| Started | Jul 05 04:37:59 PM PDT 24 |
| Finished | Jul 05 04:38:03 PM PDT 24 |
| Peak memory | 205776 kb |
| Host | smart-1aea2c45-0770-4a1e-8dc7-6da04739bb5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4087829227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.4087829227 |
| Directory | /workspace/26.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4130451859 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 66719730 ps |
| CPU time | 0.73 seconds |
| Started | Jul 05 04:38:02 PM PDT 24 |
| Finished | Jul 05 04:38:07 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-1cc473f9-1445-4c66-ab65-1ab402a9deb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4130451859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4130451859 |
| Directory | /workspace/27.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.827958866 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 55392697 ps |
| CPU time | 0.68 seconds |
| Started | Jul 05 04:38:02 PM PDT 24 |
| Finished | Jul 05 04:38:07 PM PDT 24 |
| Peak memory | 205724 kb |
| Host | smart-30040f36-d192-4058-827a-f39cdc59983a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=827958866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.827958866 |
| Directory | /workspace/28.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3131769937 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 77669202 ps |
| CPU time | 0.7 seconds |
| Started | Jul 05 04:37:58 PM PDT 24 |
| Finished | Jul 05 04:38:01 PM PDT 24 |
| Peak memory | 205736 kb |
| Host | smart-0b52ed23-b386-44b1-a08f-2b21be1736c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3131769937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3131769937 |
| Directory | /workspace/29.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.89802991 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 231343349 ps |
| CPU time | 2.32 seconds |
| Started | Jul 05 04:37:38 PM PDT 24 |
| Finished | Jul 05 04:37:42 PM PDT 24 |
| Peak memory | 205980 kb |
| Host | smart-0733e3d7-3d5d-4733-a13e-ff3fc98d3d97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=89802991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.89802991 |
| Directory | /workspace/3.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3816801525 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 743961247 ps |
| CPU time | 4.74 seconds |
| Started | Jul 05 04:37:38 PM PDT 24 |
| Finished | Jul 05 04:37:44 PM PDT 24 |
| Peak memory | 205956 kb |
| Host | smart-c021dc7b-e5d0-4acd-b7f3-740477ceea15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3816801525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3816801525 |
| Directory | /workspace/3.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1230196560 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 69797115 ps |
| CPU time | 0.87 seconds |
| Started | Jul 05 04:37:30 PM PDT 24 |
| Finished | Jul 05 04:37:34 PM PDT 24 |
| Peak memory | 205788 kb |
| Host | smart-e88167d8-308f-4953-aba9-5fc352b0110d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1230196560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1230196560 |
| Directory | /workspace/3.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.501217388 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 88175521 ps |
| CPU time | 1.21 seconds |
| Started | Jul 05 04:37:39 PM PDT 24 |
| Finished | Jul 05 04:37:42 PM PDT 24 |
| Peak memory | 214216 kb |
| Host | smart-f674ddbc-be9a-48c5-9d92-da05060ed12a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501217388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev _csr_mem_rw_with_rand_reset.501217388 |
| Directory | /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.431102401 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 116815502 ps |
| CPU time | 0.88 seconds |
| Started | Jul 05 04:37:48 PM PDT 24 |
| Finished | Jul 05 04:37:50 PM PDT 24 |
| Peak memory | 205776 kb |
| Host | smart-996aef09-9683-4d05-99bc-e3f802a3d947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=431102401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.431102401 |
| Directory | /workspace/3.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1813670584 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 46404874 ps |
| CPU time | 0.72 seconds |
| Started | Jul 05 04:37:40 PM PDT 24 |
| Finished | Jul 05 04:37:42 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-0e7eefb2-3b1b-4425-8a68-5ea5a84a55f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1813670584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1813670584 |
| Directory | /workspace/3.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2755146118 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 197071600 ps |
| CPU time | 2.33 seconds |
| Started | Jul 05 04:37:42 PM PDT 24 |
| Finished | Jul 05 04:37:45 PM PDT 24 |
| Peak memory | 214140 kb |
| Host | smart-84edd97e-f8e4-45e6-bf14-ef51be968aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2755146118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2755146118 |
| Directory | /workspace/3.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3110565860 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 219859290 ps |
| CPU time | 3.9 seconds |
| Started | Jul 05 04:37:37 PM PDT 24 |
| Finished | Jul 05 04:37:42 PM PDT 24 |
| Peak memory | 205864 kb |
| Host | smart-ba09a4b4-9817-485c-ae0e-42d41a286027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3110565860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3110565860 |
| Directory | /workspace/3.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2304395751 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 149969693 ps |
| CPU time | 1.06 seconds |
| Started | Jul 05 04:37:39 PM PDT 24 |
| Finished | Jul 05 04:37:41 PM PDT 24 |
| Peak memory | 205908 kb |
| Host | smart-19d7264d-a872-438e-ace3-033088da94c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2304395751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2304395751 |
| Directory | /workspace/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2447385885 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 257040723 ps |
| CPU time | 3.14 seconds |
| Started | Jul 05 04:37:39 PM PDT 24 |
| Finished | Jul 05 04:37:43 PM PDT 24 |
| Peak memory | 221672 kb |
| Host | smart-6ba98b97-14aa-4ae7-bc76-a0f6abfd7b91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2447385885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2447385885 |
| Directory | /workspace/3.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3047924250 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 38972505 ps |
| CPU time | 0.72 seconds |
| Started | Jul 05 04:38:00 PM PDT 24 |
| Finished | Jul 05 04:38:04 PM PDT 24 |
| Peak memory | 205800 kb |
| Host | smart-2dba2b13-0881-439f-b3dc-8a68abb8ee21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3047924250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3047924250 |
| Directory | /workspace/30.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3576483282 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 40030675 ps |
| CPU time | 0.64 seconds |
| Started | Jul 05 04:38:01 PM PDT 24 |
| Finished | Jul 05 04:38:05 PM PDT 24 |
| Peak memory | 205648 kb |
| Host | smart-a2439eba-8dd7-4577-a971-ec1a751cce4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3576483282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3576483282 |
| Directory | /workspace/31.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3641691936 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 60394370 ps |
| CPU time | 0.69 seconds |
| Started | Jul 05 04:37:57 PM PDT 24 |
| Finished | Jul 05 04:38:01 PM PDT 24 |
| Peak memory | 205732 kb |
| Host | smart-865938e3-2abe-498a-800c-4ba0e1a8abd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3641691936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3641691936 |
| Directory | /workspace/32.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4211910282 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 33415371 ps |
| CPU time | 0.7 seconds |
| Started | Jul 05 04:37:55 PM PDT 24 |
| Finished | Jul 05 04:37:58 PM PDT 24 |
| Peak memory | 205740 kb |
| Host | smart-4e9f1aa4-9574-493f-bdcb-8307e2cfe431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4211910282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.4211910282 |
| Directory | /workspace/33.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3229541432 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 35255512 ps |
| CPU time | 0.65 seconds |
| Started | Jul 05 04:38:09 PM PDT 24 |
| Finished | Jul 05 04:38:14 PM PDT 24 |
| Peak memory | 205744 kb |
| Host | smart-6973e78a-142a-4149-aeb7-d465fc66cd38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3229541432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3229541432 |
| Directory | /workspace/34.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3871901568 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 127838868 ps |
| CPU time | 0.72 seconds |
| Started | Jul 05 04:37:57 PM PDT 24 |
| Finished | Jul 05 04:38:01 PM PDT 24 |
| Peak memory | 205716 kb |
| Host | smart-cad917d9-792e-49a8-829d-a7777cbeb2c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3871901568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3871901568 |
| Directory | /workspace/35.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2714564187 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 39994168 ps |
| CPU time | 0.63 seconds |
| Started | Jul 05 04:38:01 PM PDT 24 |
| Finished | Jul 05 04:38:05 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-993694c4-5219-442f-b7c4-2f8fc73355e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2714564187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2714564187 |
| Directory | /workspace/36.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3620278417 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 37352226 ps |
| CPU time | 0.71 seconds |
| Started | Jul 05 04:37:56 PM PDT 24 |
| Finished | Jul 05 04:37:59 PM PDT 24 |
| Peak memory | 205708 kb |
| Host | smart-d185f3df-adc8-4619-8e72-2c7dc8a5508f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3620278417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3620278417 |
| Directory | /workspace/38.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.680697688 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 51793334 ps |
| CPU time | 0.71 seconds |
| Started | Jul 05 04:38:07 PM PDT 24 |
| Finished | Jul 05 04:38:12 PM PDT 24 |
| Peak memory | 205800 kb |
| Host | smart-e54d8810-30cc-4cae-b2bf-1dcde0447b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=680697688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.680697688 |
| Directory | /workspace/39.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1403083313 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 307983208 ps |
| CPU time | 3.69 seconds |
| Started | Jul 05 04:37:38 PM PDT 24 |
| Finished | Jul 05 04:37:43 PM PDT 24 |
| Peak memory | 205944 kb |
| Host | smart-67ebcfe8-56c5-4423-9acc-fdf470afbc20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1403083313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1403083313 |
| Directory | /workspace/4.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1253856767 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 688963033 ps |
| CPU time | 4.6 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:50 PM PDT 24 |
| Peak memory | 205896 kb |
| Host | smart-63726428-3151-4fe2-9911-ebd567954139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1253856767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1253856767 |
| Directory | /workspace/4.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1970464000 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 73008911 ps |
| CPU time | 0.91 seconds |
| Started | Jul 05 04:37:36 PM PDT 24 |
| Finished | Jul 05 04:37:38 PM PDT 24 |
| Peak memory | 205820 kb |
| Host | smart-bc4dea91-95f0-431a-b880-f3ed1b4aab38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1970464000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1970464000 |
| Directory | /workspace/4.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2390247311 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 90436528 ps |
| CPU time | 1.35 seconds |
| Started | Jul 05 04:37:35 PM PDT 24 |
| Finished | Jul 05 04:37:37 PM PDT 24 |
| Peak memory | 214232 kb |
| Host | smart-bb0fa5d1-77ea-47a1-aa2e-74ae1119efad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390247311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde v_csr_mem_rw_with_rand_reset.2390247311 |
| Directory | /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3196219759 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 45627960 ps |
| CPU time | 0.96 seconds |
| Started | Jul 05 04:37:38 PM PDT 24 |
| Finished | Jul 05 04:37:40 PM PDT 24 |
| Peak memory | 205996 kb |
| Host | smart-6b60d8a9-94d7-481f-b580-16a022fa7fb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3196219759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3196219759 |
| Directory | /workspace/4.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4224631024 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 38909201 ps |
| CPU time | 0.65 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:47 PM PDT 24 |
| Peak memory | 205812 kb |
| Host | smart-b5a18e0a-8bb7-4e88-834d-19d55d8dfd13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4224631024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.4224631024 |
| Directory | /workspace/4.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1431218926 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 81566421 ps |
| CPU time | 2.22 seconds |
| Started | Jul 05 04:37:41 PM PDT 24 |
| Finished | Jul 05 04:37:44 PM PDT 24 |
| Peak memory | 214140 kb |
| Host | smart-a5f6a1fd-1cd4-46fb-b799-a6155244a709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1431218926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1431218926 |
| Directory | /workspace/4.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3929723266 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 521650143 ps |
| CPU time | 4.5 seconds |
| Started | Jul 05 04:37:40 PM PDT 24 |
| Finished | Jul 05 04:37:45 PM PDT 24 |
| Peak memory | 205976 kb |
| Host | smart-f3923719-23b8-4c42-92ce-b4f514241f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3929723266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3929723266 |
| Directory | /workspace/4.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3616798699 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 109634827 ps |
| CPU time | 1.15 seconds |
| Started | Jul 05 04:37:50 PM PDT 24 |
| Finished | Jul 05 04:37:53 PM PDT 24 |
| Peak memory | 205920 kb |
| Host | smart-eb48ec38-a637-4142-98d0-04395c00e316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3616798699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3616798699 |
| Directory | /workspace/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2482332866 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 379627173 ps |
| CPU time | 3.68 seconds |
| Started | Jul 05 04:37:37 PM PDT 24 |
| Finished | Jul 05 04:37:42 PM PDT 24 |
| Peak memory | 221812 kb |
| Host | smart-75ae3b15-6f53-4519-8d98-53046ac0c7b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2482332866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2482332866 |
| Directory | /workspace/4.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2170876648 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1489835527 ps |
| CPU time | 5.17 seconds |
| Started | Jul 05 04:37:43 PM PDT 24 |
| Finished | Jul 05 04:37:49 PM PDT 24 |
| Peak memory | 206016 kb |
| Host | smart-56d13f56-8591-4aee-8468-387ae371b4bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2170876648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2170876648 |
| Directory | /workspace/4.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4220452766 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 30071679 ps |
| CPU time | 0.67 seconds |
| Started | Jul 05 04:38:04 PM PDT 24 |
| Finished | Jul 05 04:38:09 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-88872929-50f7-410b-b53d-797dbf61d019 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4220452766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.4220452766 |
| Directory | /workspace/40.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2244184791 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 48298847 ps |
| CPU time | 0.66 seconds |
| Started | Jul 05 04:38:01 PM PDT 24 |
| Finished | Jul 05 04:38:05 PM PDT 24 |
| Peak memory | 205664 kb |
| Host | smart-e2457e54-9bca-4036-be77-cc1fb45096a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2244184791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2244184791 |
| Directory | /workspace/41.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1420216221 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 47938127 ps |
| CPU time | 0.69 seconds |
| Started | Jul 05 04:37:56 PM PDT 24 |
| Finished | Jul 05 04:38:00 PM PDT 24 |
| Peak memory | 205712 kb |
| Host | smart-8aee871e-57bd-460b-a9fe-59727bcc96df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1420216221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1420216221 |
| Directory | /workspace/42.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3796722323 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 67883836 ps |
| CPU time | 0.71 seconds |
| Started | Jul 05 04:38:04 PM PDT 24 |
| Finished | Jul 05 04:38:08 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-d1e891fb-952b-4068-9d61-3ed5f4bfebe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3796722323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3796722323 |
| Directory | /workspace/43.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2299410200 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 47783344 ps |
| CPU time | 0.66 seconds |
| Started | Jul 05 04:37:57 PM PDT 24 |
| Finished | Jul 05 04:38:01 PM PDT 24 |
| Peak memory | 205740 kb |
| Host | smart-68057ff6-f8e1-4827-9b70-82c072c52e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2299410200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2299410200 |
| Directory | /workspace/44.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4278949654 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 31915053 ps |
| CPU time | 0.66 seconds |
| Started | Jul 05 04:38:05 PM PDT 24 |
| Finished | Jul 05 04:38:10 PM PDT 24 |
| Peak memory | 205720 kb |
| Host | smart-41a41fdb-11e7-4a94-92a1-7085df917e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4278949654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.4278949654 |
| Directory | /workspace/45.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3150766890 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 41892890 ps |
| CPU time | 0.67 seconds |
| Started | Jul 05 04:38:01 PM PDT 24 |
| Finished | Jul 05 04:38:05 PM PDT 24 |
| Peak memory | 205740 kb |
| Host | smart-53bb066a-3c98-4cca-83d4-1d83fe56b980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3150766890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3150766890 |
| Directory | /workspace/46.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2286346547 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 39983180 ps |
| CPU time | 0.72 seconds |
| Started | Jul 05 04:37:55 PM PDT 24 |
| Finished | Jul 05 04:37:57 PM PDT 24 |
| Peak memory | 205740 kb |
| Host | smart-4be2a712-c71c-4b55-b89e-30d349b010e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2286346547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2286346547 |
| Directory | /workspace/48.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.477648254 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 50944415 ps |
| CPU time | 0.68 seconds |
| Started | Jul 05 04:37:59 PM PDT 24 |
| Finished | Jul 05 04:38:02 PM PDT 24 |
| Peak memory | 205672 kb |
| Host | smart-6781dc1a-3e14-42b1-83f9-979df4914306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=477648254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.477648254 |
| Directory | /workspace/49.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1336574212 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 86171663 ps |
| CPU time | 1.51 seconds |
| Started | Jul 05 04:37:37 PM PDT 24 |
| Finished | Jul 05 04:37:39 PM PDT 24 |
| Peak memory | 214200 kb |
| Host | smart-291fefc7-bf10-454e-adbd-d31879504892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336574212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde v_csr_mem_rw_with_rand_reset.1336574212 |
| Directory | /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.342777846 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 84140170 ps |
| CPU time | 1.03 seconds |
| Started | Jul 05 04:37:56 PM PDT 24 |
| Finished | Jul 05 04:38:00 PM PDT 24 |
| Peak memory | 206000 kb |
| Host | smart-9b6a1a70-89e1-410e-ba5b-8f6421dba05a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=342777846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.342777846 |
| Directory | /workspace/5.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3085246279 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 82093047 ps |
| CPU time | 0.73 seconds |
| Started | Jul 05 04:37:43 PM PDT 24 |
| Finished | Jul 05 04:37:46 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-3fb4e18c-31e3-4af7-8440-c6adabccdd0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3085246279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3085246279 |
| Directory | /workspace/5.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1462579400 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 332601805 ps |
| CPU time | 1.79 seconds |
| Started | Jul 05 04:37:38 PM PDT 24 |
| Finished | Jul 05 04:37:41 PM PDT 24 |
| Peak memory | 205912 kb |
| Host | smart-81011c4b-a7b9-4e7a-81ff-87c3c8ffa146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1462579400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1462579400 |
| Directory | /workspace/5.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2816509527 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 152725137 ps |
| CPU time | 3.69 seconds |
| Started | Jul 05 04:37:37 PM PDT 24 |
| Finished | Jul 05 04:37:42 PM PDT 24 |
| Peak memory | 214200 kb |
| Host | smart-7a488725-ff28-4654-bc08-237f046de026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2816509527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2816509527 |
| Directory | /workspace/5.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2317571737 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 112732358 ps |
| CPU time | 1.03 seconds |
| Started | Jul 05 04:37:46 PM PDT 24 |
| Finished | Jul 05 04:37:49 PM PDT 24 |
| Peak memory | 206012 kb |
| Host | smart-0fb4d239-92ef-4b0c-9ee9-e11eb491c78d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2317571737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2317571737 |
| Directory | /workspace/6.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3319729921 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 105868498 ps |
| CPU time | 1.06 seconds |
| Started | Jul 05 04:37:39 PM PDT 24 |
| Finished | Jul 05 04:37:41 PM PDT 24 |
| Peak memory | 205828 kb |
| Host | smart-36de7f64-6017-4114-8b68-092a161e26f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3319729921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3319729921 |
| Directory | /workspace/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1467021312 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 214520762 ps |
| CPU time | 1.83 seconds |
| Started | Jul 05 04:37:38 PM PDT 24 |
| Finished | Jul 05 04:37:41 PM PDT 24 |
| Peak memory | 221816 kb |
| Host | smart-9edeab55-f930-4143-a9ec-d440bd2ff1f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1467021312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1467021312 |
| Directory | /workspace/6.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3176445232 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 106570695 ps |
| CPU time | 1.19 seconds |
| Started | Jul 05 04:37:45 PM PDT 24 |
| Finished | Jul 05 04:37:49 PM PDT 24 |
| Peak memory | 214196 kb |
| Host | smart-c79afe22-2906-4433-92ef-651db518717e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176445232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde v_csr_mem_rw_with_rand_reset.3176445232 |
| Directory | /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.690429652 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 63344955 ps |
| CPU time | 0.88 seconds |
| Started | Jul 05 04:37:46 PM PDT 24 |
| Finished | Jul 05 04:37:49 PM PDT 24 |
| Peak memory | 205780 kb |
| Host | smart-323346d6-9f2b-448f-bdae-5895eb78de42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=690429652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.690429652 |
| Directory | /workspace/7.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.297615399 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 59942008 ps |
| CPU time | 0.69 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:47 PM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-e2ba3042-a6b9-4125-a18e-1155e1eb2d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=297615399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.297615399 |
| Directory | /workspace/7.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3492365 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 212822437 ps |
| CPU time | 1.72 seconds |
| Started | Jul 05 04:37:47 PM PDT 24 |
| Finished | Jul 05 04:37:51 PM PDT 24 |
| Peak memory | 205948 kb |
| Host | smart-4eea52c4-3649-4eeb-8df1-fc08895db05f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3492365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3492365 |
| Directory | /workspace/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1169650806 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 360175705 ps |
| CPU time | 3.68 seconds |
| Started | Jul 05 04:37:54 PM PDT 24 |
| Finished | Jul 05 04:38:00 PM PDT 24 |
| Peak memory | 221736 kb |
| Host | smart-0abcf203-7875-4f0e-9a8e-0bc008c5bc29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1169650806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1169650806 |
| Directory | /workspace/7.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.62659258 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1228948349 ps |
| CPU time | 5.6 seconds |
| Started | Jul 05 04:37:55 PM PDT 24 |
| Finished | Jul 05 04:38:03 PM PDT 24 |
| Peak memory | 205972 kb |
| Host | smart-042edf9f-853e-4e32-ae91-5fef5d7eba3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=62659258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.62659258 |
| Directory | /workspace/7.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2413252695 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 61659522 ps |
| CPU time | 1.26 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 214296 kb |
| Host | smart-b95f49b6-3f2d-4640-b6ac-9888b9f4d5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413252695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde v_csr_mem_rw_with_rand_reset.2413252695 |
| Directory | /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3938774373 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 48342424 ps |
| CPU time | 1 seconds |
| Started | Jul 05 04:37:55 PM PDT 24 |
| Finished | Jul 05 04:37:58 PM PDT 24 |
| Peak memory | 205992 kb |
| Host | smart-44e409a4-8b54-4e20-81cc-737a8840e962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3938774373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3938774373 |
| Directory | /workspace/8.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2407341465 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 35002137 ps |
| CPU time | 0.68 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:47 PM PDT 24 |
| Peak memory | 205776 kb |
| Host | smart-647d946d-661b-4f80-af74-68ee60ba9cd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2407341465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2407341465 |
| Directory | /workspace/8.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.976172351 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 153829173 ps |
| CPU time | 1.49 seconds |
| Started | Jul 05 04:37:48 PM PDT 24 |
| Finished | Jul 05 04:37:51 PM PDT 24 |
| Peak memory | 205868 kb |
| Host | smart-4bbe0bef-71dc-4f0c-921a-634ba1031c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=976172351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.976172351 |
| Directory | /workspace/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1283430642 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 138114479 ps |
| CPU time | 2.32 seconds |
| Started | Jul 05 04:37:58 PM PDT 24 |
| Finished | Jul 05 04:38:03 PM PDT 24 |
| Peak memory | 214224 kb |
| Host | smart-96310de2-18bf-43a1-b948-7e9ce591f2ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1283430642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1283430642 |
| Directory | /workspace/8.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.47686961 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 818208375 ps |
| CPU time | 4.1 seconds |
| Started | Jul 05 04:38:00 PM PDT 24 |
| Finished | Jul 05 04:38:08 PM PDT 24 |
| Peak memory | 206020 kb |
| Host | smart-9ed3819e-5729-4309-8316-e0511f012ac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=47686961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.47686961 |
| Directory | /workspace/8.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3947646322 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 146674439 ps |
| CPU time | 1.41 seconds |
| Started | Jul 05 04:37:45 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 214228 kb |
| Host | smart-3eeeabe1-527f-4f28-90b9-272721ccb63c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947646322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde v_csr_mem_rw_with_rand_reset.3947646322 |
| Directory | /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2302830677 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 163604386 ps |
| CPU time | 0.91 seconds |
| Started | Jul 05 04:37:42 PM PDT 24 |
| Finished | Jul 05 04:37:45 PM PDT 24 |
| Peak memory | 205716 kb |
| Host | smart-da1dbb2b-fba5-42ee-b0d3-b911e3b3bc3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2302830677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2302830677 |
| Directory | /workspace/9.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3708510849 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 39799527 ps |
| CPU time | 0.67 seconds |
| Started | Jul 05 04:37:48 PM PDT 24 |
| Finished | Jul 05 04:37:51 PM PDT 24 |
| Peak memory | 205736 kb |
| Host | smart-ff06e757-c0e9-4461-ba3e-67ba7765644a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3708510849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3708510849 |
| Directory | /workspace/9.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.144499821 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 66568582 ps |
| CPU time | 1.18 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:47 PM PDT 24 |
| Peak memory | 205880 kb |
| Host | smart-d5cf975b-ee1b-4958-9193-85ec1e9b8109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=144499821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.144499821 |
| Directory | /workspace/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4122433504 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 202079276 ps |
| CPU time | 1.82 seconds |
| Started | Jul 05 04:37:44 PM PDT 24 |
| Finished | Jul 05 04:37:48 PM PDT 24 |
| Peak memory | 206024 kb |
| Host | smart-eab90a8a-c786-482b-8d7a-9ab9706078e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4122433504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4122433504 |
| Directory | /workspace/9.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2557096237 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 350849133 ps |
| CPU time | 2.53 seconds |
| Started | Jul 05 04:37:42 PM PDT 24 |
| Finished | Jul 05 04:37:46 PM PDT 24 |
| Peak memory | 205908 kb |
| Host | smart-a72d4e15-0e23-4353-affd-4a4f8bacc160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2557096237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2557096237 |
| Directory | /workspace/9.usbdev_tl_intg_err/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |