Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	359	1		T2	8		T7	8		T9	5
all_pins[1]	359	1		T2	8		T7	8		T9	5
all_pins[2]	359	1		T2	8		T7	8		T9	5
all_pins[3]	359	1		T2	8		T7	8		T9	5
all_pins[4]	359	1		T2	8		T7	8		T9	5
all_pins[5]	359	1		T2	8		T7	8		T9	5
all_pins[6]	359	1		T2	8		T7	8		T9	5
all_pins[7]	359	1		T2	8		T7	8		T9	5
all_pins[8]	359	1		T2	8		T7	8		T9	5
all_pins[9]	359	1		T2	8		T7	8		T9	5
all_pins[10]	359	1		T2	8		T7	8		T9	5
all_pins[11]	359	1		T2	8		T7	8		T9	5
all_pins[12]	359	1		T2	8		T7	8		T9	5
all_pins[13]	359	1		T2	8		T7	8		T9	5
all_pins[14]	359	1		T2	8		T7	8		T9	5
all_pins[15]	359	1		T2	8		T7	8		T9	5
all_pins[16]	359	1		T2	8		T7	8		T9	5
all_pins[17]	359	1		T2	8		T7	8		T9	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5323	1		T2	121		T7	110		T9	79
values[0x1]	1139	1		T2	23		T7	34		T9	11
transitions[0x0=>0x1]	823	1		T2	19		T7	26		T9	8
transitions[0x1=>0x0]	835	1		T2	20		T7	26		T9	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	300	1		T2	7		T7	8		T9	5
all_pins[0]	values[0x1]	59	1		T2	1		T13	4		T32	1
all_pins[0]	transitions[0x0=>0x1]	43	1		T2	1		T13	3		T32	1
all_pins[0]	transitions[0x1=>0x0]	48	1		T2	1		T7	2		T9	1
all_pins[1]	values[0x0]	295	1		T2	7		T7	6		T9	4
all_pins[1]	values[0x1]	64	1		T2	1		T7	2		T9	1
all_pins[1]	transitions[0x0=>0x1]	43	1		T2	1		T7	1		T9	1
all_pins[1]	transitions[0x1=>0x0]	70	1		T2	3		T7	2		T8	1
all_pins[2]	values[0x0]	268	1		T2	5		T7	5		T9	5
all_pins[2]	values[0x1]	91	1		T2	3		T7	3		T8	2
all_pins[2]	transitions[0x0=>0x1]	66	1		T2	3		T7	3		T8	2
all_pins[2]	transitions[0x1=>0x0]	44	1		T9	1		T8	1		T34	2
all_pins[3]	values[0x0]	290	1		T2	8		T7	8		T9	4
all_pins[3]	values[0x1]	69	1		T9	1		T8	1		T34	4
all_pins[3]	transitions[0x0=>0x1]	51	1		T8	1		T34	3		T72	2
all_pins[3]	transitions[0x1=>0x0]	38	1		T2	2		T8	1		T13	1
all_pins[4]	values[0x0]	303	1		T2	6		T7	8		T9	4
all_pins[4]	values[0x1]	56	1		T2	2		T9	1		T8	1
all_pins[4]	transitions[0x0=>0x1]	39	1		T2	1		T9	1		T8	1
all_pins[4]	transitions[0x1=>0x0]	43	1		T2	2		T7	2		T9	1
all_pins[5]	values[0x0]	299	1		T2	5		T7	6		T9	4
all_pins[5]	values[0x1]	60	1		T2	3		T7	2		T9	1
all_pins[5]	transitions[0x0=>0x1]	48	1		T2	3		T7	2		T9	1
all_pins[5]	transitions[0x1=>0x0]	52	1		T2	1		T7	1		T9	2
all_pins[6]	values[0x0]	295	1		T2	7		T7	7		T9	3
all_pins[6]	values[0x1]	64	1		T2	1		T7	1		T9	2
all_pins[6]	transitions[0x0=>0x1]	48	1		T2	1		T7	1		T9	2
all_pins[6]	transitions[0x1=>0x0]	36	1		T2	1		T7	2		T8	3
all_pins[7]	values[0x0]	307	1		T2	7		T7	6		T9	5
all_pins[7]	values[0x1]	52	1		T2	1		T7	2		T8	3
all_pins[7]	transitions[0x0=>0x1]	42	1		T2	1		T7	1		T8	3
all_pins[7]	transitions[0x1=>0x0]	46	1		T2	2		T7	3		T8	1
all_pins[8]	values[0x0]	303	1		T2	6		T7	4		T9	5
all_pins[8]	values[0x1]	56	1		T2	2		T7	4		T8	1
all_pins[8]	transitions[0x0=>0x1]	44	1		T2	2		T7	3		T8	1
all_pins[8]	transitions[0x1=>0x0]	46	1		T2	2		T7	1		T13	2
all_pins[9]	values[0x0]	301	1		T2	6		T7	6		T9	5
all_pins[9]	values[0x1]	58	1		T2	2		T7	2		T13	2
all_pins[9]	transitions[0x0=>0x1]	43	1		T2	1		T13	2		T71	2
all_pins[9]	transitions[0x1=>0x0]	55	1		T2	1		T7	3		T9	1
all_pins[10]	values[0x0]	289	1		T2	6		T7	3		T9	4
all_pins[10]	values[0x1]	70	1		T2	2		T7	5		T9	1
all_pins[10]	transitions[0x0=>0x1]	49	1		T2	1		T7	4		T9	1
all_pins[10]	transitions[0x1=>0x0]	42	1		T2	1		T7	1		T9	1
all_pins[11]	values[0x0]	296	1		T2	6		T7	6		T9	4
all_pins[11]	values[0x1]	63	1		T2	2		T7	2		T9	1
all_pins[11]	transitions[0x0=>0x1]	48	1		T2	2		T7	2		T8	1
all_pins[11]	transitions[0x1=>0x0]	43	1		T8	2		T13	3		T34	4
all_pins[12]	values[0x0]	301	1		T2	8		T7	8		T9	4
all_pins[12]	values[0x1]	58	1		T9	1		T8	2		T13	3
all_pins[12]	transitions[0x0=>0x1]	38	1		T9	1		T8	2		T13	1
all_pins[12]	transitions[0x1=>0x0]	57	1		T7	2		T35	1		T72	2
all_pins[13]	values[0x0]	282	1		T2	8		T7	6		T9	5
all_pins[13]	values[0x1]	77	1		T7	2		T13	2		T34	1
all_pins[13]	transitions[0x0=>0x1]	52	1		T7	2		T13	2		T34	1
all_pins[13]	transitions[0x1=>0x0]	42	1		T2	1		T7	4		T9	1
all_pins[14]	values[0x0]	292	1		T2	7		T7	4		T9	4
all_pins[14]	values[0x1]	67	1		T2	1		T7	4		T9	1
all_pins[14]	transitions[0x0=>0x1]	50	1		T2	1		T7	4		T8	1
all_pins[14]	transitions[0x1=>0x0]	45	1		T2	1		T8	4		T13	1
all_pins[15]	values[0x0]	297	1		T2	7		T7	8		T9	4
all_pins[15]	values[0x1]	62	1		T2	1		T9	1		T8	4
all_pins[15]	transitions[0x0=>0x1]	45	1		T2	1		T9	1		T8	4
all_pins[15]	transitions[0x1=>0x0]	46	1		T7	3		T13	1		T34	2
all_pins[16]	values[0x0]	296	1		T2	8		T7	5		T9	5
all_pins[16]	values[0x1]	63	1		T7	3		T13	1		T34	3
all_pins[16]	transitions[0x0=>0x1]	47	1		T7	1		T34	2		T35	2
all_pins[16]	transitions[0x1=>0x0]	34	1		T2	1		T8	1		T13	1
all_pins[17]	values[0x0]	309	1		T2	7		T7	6		T9	5
all_pins[17]	values[0x1]	50	1		T2	1		T7	2		T8	1
all_pins[17]	transitions[0x0=>0x1]	27	1		T7	2		T47	2		T48	1
all_pins[17]	transitions[0x1=>0x0]	48	1		T2	1		T13	2		T32	1