Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T2	7		T7	7		T9	4
all_values[1]	269	1		T2	7		T7	7		T9	4
all_values[2]	269	1		T2	7		T7	7		T9	4
all_values[3]	269	1		T2	7		T7	7		T9	4
all_values[4]	269	1		T2	7		T7	7		T9	4
all_values[5]	269	1		T2	7		T7	7		T9	4
all_values[6]	269	1		T2	7		T7	7		T9	4
all_values[7]	269	1		T2	7		T7	7		T9	4
all_values[8]	269	1		T2	7		T7	7		T9	4
all_values[9]	269	1		T2	7		T7	7		T9	4
all_values[10]	269	1		T2	7		T7	7		T9	4
all_values[11]	269	1		T2	7		T7	7		T9	4
all_values[12]	269	1		T2	7		T7	7		T9	4
all_values[13]	269	1		T2	7		T7	7		T9	4
all_values[14]	269	1		T2	7		T7	7		T9	4
all_values[15]	269	1		T2	7		T7	7		T9	4
all_values[16]	269	1		T2	7		T7	7		T9	4
all_values[17]	269	1		T2	7		T7	7		T9	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2613	1		T2	80		T7	72		T9	33
auto[1]	2229	1		T2	46		T7	54		T9	39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	851	1		T2	17		T7	7		T9	21
auto[1]	3991	1		T2	109		T7	119		T9	51

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2836	1		T2	78		T7	65		T9	51
auto[1]	2006	1		T2	48		T7	61		T9	21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	26	1		T2	1		T9	4		T8	2
all_values[0]	auto[0]	auto[0]	auto[1]	52	1		T2	2		T7	1		T8	1
all_values[0]	auto[0]	auto[1]	auto[0]	19	1		T8	2		T35	1		T71	3
all_values[0]	auto[0]	auto[1]	auto[1]	57	1		T2	1		T7	4		T13	2
all_values[0]	auto[1]	auto[0]	auto[1]	67	1		T2	2		T7	2		T8	2
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T2	1		T13	2		T32	1
all_values[1]	auto[0]	auto[0]	auto[0]	28	1		T2	1		T35	1		T78	1
all_values[1]	auto[0]	auto[0]	auto[1]	45	1		T2	1		T7	2		T9	1
all_values[1]	auto[0]	auto[1]	auto[0]	12	1		T71	1		T75	2		T76	1
all_values[1]	auto[0]	auto[1]	auto[1]	63	1		T2	1		T7	1		T9	1
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T2	4		T7	4		T9	1
all_values[1]	auto[1]	auto[1]	auto[1]	55	1		T9	1		T8	2		T13	3
all_values[2]	auto[0]	auto[0]	auto[0]	35	1		T7	1		T9	1		T13	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1		T2	2		T7	1		T9	1
all_values[2]	auto[0]	auto[1]	auto[0]	13	1		T13	1		T32	1		T45	2
all_values[2]	auto[0]	auto[1]	auto[1]	57	1		T2	1		T7	2		T8	3
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T2	2		T9	2		T8	3
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T2	2		T7	3		T13	1
all_values[3]	auto[0]	auto[0]	auto[0]	25	1		T2	3		T13	1		T35	1
all_values[3]	auto[0]	auto[0]	auto[1]	58	1		T7	3		T8	3		T13	2
all_values[3]	auto[0]	auto[1]	auto[0]	17	1		T2	1		T34	2		T75	1
all_values[3]	auto[0]	auto[1]	auto[1]	54	1		T2	1		T7	1		T9	1
all_values[3]	auto[1]	auto[0]	auto[1]	68	1		T2	2		T7	3		T13	1
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T9	3		T8	1		T13	1
all_values[4]	auto[0]	auto[0]	auto[0]	35	1		T9	1		T35	2		T71	1
all_values[4]	auto[0]	auto[0]	auto[1]	46	1		T2	1		T7	1		T9	1
all_values[4]	auto[0]	auto[1]	auto[0]	24	1		T8	2		T13	2		T71	3
all_values[4]	auto[0]	auto[1]	auto[1]	54	1		T2	3		T7	3		T13	2
all_values[4]	auto[1]	auto[0]	auto[1]	55	1		T2	1		T7	2		T8	3
all_values[4]	auto[1]	auto[1]	auto[1]	55	1		T2	2		T7	1		T9	2
all_values[5]	auto[0]	auto[0]	auto[0]	34	1		T8	2		T32	4		T35	1
all_values[5]	auto[0]	auto[0]	auto[1]	50	1		T2	1		T7	3		T9	1
all_values[5]	auto[0]	auto[1]	auto[0]	18	1		T8	3		T34	1		T35	1
all_values[5]	auto[0]	auto[1]	auto[1]	66	1		T2	3		T7	1		T9	2
all_values[5]	auto[1]	auto[0]	auto[1]	59	1		T2	1		T7	3		T8	1
all_values[5]	auto[1]	auto[1]	auto[1]	42	1		T2	2		T9	1		T13	2
all_values[6]	auto[0]	auto[0]	auto[0]	23	1		T2	1		T9	1		T13	1
all_values[6]	auto[0]	auto[0]	auto[1]	63	1		T2	4		T7	4		T8	2
all_values[6]	auto[0]	auto[1]	auto[0]	20	1		T8	1		T13	1		T34	2
all_values[6]	auto[0]	auto[1]	auto[1]	53	1		T9	1		T8	2		T13	3
all_values[6]	auto[1]	auto[0]	auto[1]	60	1		T2	1		T7	2		T32	2
all_values[6]	auto[1]	auto[1]	auto[1]	50	1		T2	1		T7	1		T9	2
all_values[7]	auto[0]	auto[0]	auto[0]	25	1		T2	3		T13	1		T32	1
all_values[7]	auto[0]	auto[0]	auto[1]	66	1		T7	3		T9	1		T8	1
all_values[7]	auto[0]	auto[1]	auto[0]	14	1		T2	1		T9	2		T45	1
all_values[7]	auto[0]	auto[1]	auto[1]	57	1		T2	2		T7	1		T8	1
all_values[7]	auto[1]	auto[0]	auto[1]	51	1		T7	1		T8	1		T13	1
all_values[7]	auto[1]	auto[1]	auto[1]	56	1		T2	1		T7	2		T9	1
all_values[8]	auto[0]	auto[0]	auto[0]	38	1		T9	1		T35	4		T72	3
all_values[8]	auto[0]	auto[0]	auto[1]	51	1		T2	3		T7	1		T9	1
all_values[8]	auto[0]	auto[1]	auto[0]	12	1		T32	1		T71	4		T72	1
all_values[8]	auto[0]	auto[1]	auto[1]	52	1		T7	1		T9	1		T8	1
all_values[8]	auto[1]	auto[0]	auto[1]	66	1		T2	4		T7	1		T9	1
all_values[8]	auto[1]	auto[1]	auto[1]	50	1		T7	4		T8	1		T13	1
all_values[9]	auto[0]	auto[0]	auto[0]	36	1		T7	1		T9	2		T34	1
all_values[9]	auto[0]	auto[0]	auto[1]	53	1		T8	3		T13	1		T32	2
all_values[9]	auto[0]	auto[1]	auto[0]	24	1		T9	2		T8	1		T34	3
all_values[9]	auto[0]	auto[1]	auto[1]	57	1		T2	4		T7	2		T8	2
all_values[9]	auto[1]	auto[0]	auto[1]	55	1		T2	2		T7	2		T13	5
all_values[9]	auto[1]	auto[1]	auto[1]	44	1		T2	1		T7	2		T8	1
all_values[10]	auto[0]	auto[0]	auto[0]	28	1		T34	1		T35	1		T79	1
all_values[10]	auto[0]	auto[0]	auto[1]	50	1		T2	3		T13	2		T32	1
all_values[10]	auto[0]	auto[1]	auto[0]	17	1		T32	2		T35	1		T72	3
all_values[10]	auto[0]	auto[1]	auto[1]	63	1		T2	1		T7	2		T9	3
all_values[10]	auto[1]	auto[0]	auto[1]	51	1		T2	2		T7	3		T8	1
all_values[10]	auto[1]	auto[1]	auto[1]	60	1		T2	1		T7	2		T9	1
all_values[11]	auto[0]	auto[0]	auto[0]	36	1		T7	1		T9	1		T32	1
all_values[11]	auto[0]	auto[0]	auto[1]	55	1		T2	3		T7	2		T9	1
all_values[11]	auto[0]	auto[1]	auto[0]	15	1		T13	1		T35	1		T71	1
all_values[11]	auto[0]	auto[1]	auto[1]	51	1		T2	1		T7	2		T9	1
all_values[11]	auto[1]	auto[0]	auto[1]	66	1		T2	1		T7	1		T8	3
all_values[11]	auto[1]	auto[1]	auto[1]	46	1		T2	2		T7	1		T9	1
all_values[12]	auto[0]	auto[0]	auto[0]	35	1		T2	1		T35	1		T79	1
all_values[12]	auto[0]	auto[0]	auto[1]	46	1		T2	1		T7	2		T9	1
all_values[12]	auto[0]	auto[1]	auto[0]	14	1		T2	1		T35	1		T76	1
all_values[12]	auto[0]	auto[1]	auto[1]	61	1		T2	2		T7	1		T9	2
all_values[12]	auto[1]	auto[0]	auto[1]	62	1		T2	2		T7	3		T9	1
all_values[12]	auto[1]	auto[1]	auto[1]	51	1		T7	1		T8	4		T13	3
all_values[13]	auto[0]	auto[0]	auto[0]	25	1		T2	1		T41	1		T47	1
all_values[13]	auto[0]	auto[0]	auto[1]	52	1		T2	2		T7	2		T9	2
all_values[13]	auto[0]	auto[1]	auto[0]	14	1		T77	3		T76	2		T80	2
all_values[13]	auto[0]	auto[1]	auto[1]	57	1		T9	1		T13	1		T34	2
all_values[13]	auto[1]	auto[0]	auto[1]	67	1		T2	4		T7	4		T8	5
all_values[13]	auto[1]	auto[1]	auto[1]	54	1		T7	1		T9	1		T34	2
all_values[14]	auto[0]	auto[0]	auto[0]	27	1		T7	1		T32	1		T43	1
all_values[14]	auto[0]	auto[0]	auto[1]	56	1		T2	3		T9	1		T8	1
all_values[14]	auto[0]	auto[1]	auto[0]	22	1		T7	1		T9	1		T8	2
all_values[14]	auto[0]	auto[1]	auto[1]	55	1		T2	3		T7	1		T9	1
all_values[14]	auto[1]	auto[0]	auto[1]	68	1		T2	1		T8	2		T13	2
all_values[14]	auto[1]	auto[1]	auto[1]	41	1		T7	4		T9	1		T34	1
all_values[15]	auto[0]	auto[0]	auto[0]	26	1		T2	1		T7	1		T9	1
all_values[15]	auto[0]	auto[0]	auto[1]	59	1		T2	1		T7	4		T13	3
all_values[15]	auto[0]	auto[1]	auto[0]	16	1		T7	1		T8	1		T35	1
all_values[15]	auto[0]	auto[1]	auto[1]	48	1		T2	4		T9	2		T8	2
all_values[15]	auto[1]	auto[0]	auto[1]	63	1		T8	1		T13	2		T34	4
all_values[15]	auto[1]	auto[1]	auto[1]	57	1		T2	1		T7	1		T9	1
all_values[16]	auto[0]	auto[0]	auto[0]	27	1		T2	1		T9	2		T13	1
all_values[16]	auto[0]	auto[0]	auto[1]	61	1		T2	4		T7	1		T8	3
all_values[16]	auto[0]	auto[1]	auto[0]	24	1		T2	1		T9	2		T8	1
all_values[16]	auto[0]	auto[1]	auto[1]	55	1		T7	3		T8	2		T13	1
all_values[16]	auto[1]	auto[0]	auto[1]	55	1		T2	1		T7	1		T13	2
all_values[16]	auto[1]	auto[1]	auto[1]	47	1		T7	2		T8	1		T13	1
all_values[17]	auto[0]	auto[0]	auto[0]	23	1		T71	2		T41	1		T45	2
all_values[17]	auto[0]	auto[0]	auto[1]	61	1		T2	2		T7	2		T9	2
all_values[17]	auto[0]	auto[1]	auto[0]	24	1		T13	1		T71	2		T45	2
all_values[17]	auto[0]	auto[1]	auto[1]	51	1		T2	1		T7	1		T9	1
all_values[17]	auto[1]	auto[0]	auto[1]	62	1		T2	4		T7	3		T9	1
all_values[17]	auto[1]	auto[1]	auto[1]	48	1		T7	1		T8	2		T13	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal