Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14858018	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15520140	1		T1	151		T2	5		T3	13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29890051	1		T1	150		T2	4		T3	9
values[0x0]	243413	1		T1	48		T2	2		T3	6
values[0x1]	244694	1		T1	29		T2	5		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11847383	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18530775	1		T1	172		T2	7		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	110867	1		T1	1		T31	9		T6	385
valid_sources[0x01]	80561	1		T31	12		T6	417		T45	96
valid_sources[0x02]	82138	1		T1	2		T31	17		T6	468
valid_sources[0x03]	81255	1		T1	1		T31	5		T6	375
valid_sources[0x04]	80562	1		T1	2		T31	14		T6	365
valid_sources[0x05]	119228	1		T1	2		T31	17		T6	413
valid_sources[0x06]	83234	1		T31	27		T6	400		T45	87
valid_sources[0x07]	83071	1		T31	10		T6	475		T37	4
valid_sources[0x08]	82980	1		T1	1		T31	18		T33	1
valid_sources[0x09]	103765	1		T38	2		T31	11		T6	407
valid_sources[0x0a]	146078	1		T1	1		T31	15		T6	372
valid_sources[0x0b]	292209	1		T31	7		T6	418		T45	122
valid_sources[0x0c]	113589	1		T1	2		T31	5		T6	378
valid_sources[0x0d]	81696	1		T1	2		T31	7		T6	378
valid_sources[0x0e]	142337	1		T1	1		T31	20		T33	1
valid_sources[0x0f]	81282	1		T31	9		T6	417		T45	115
valid_sources[0x10]	81339	1		T1	1		T31	13		T6	385
valid_sources[0x11]	82214	1		T1	1		T28	3		T38	2
valid_sources[0x12]	80520	1		T1	2		T31	14		T6	443
valid_sources[0x13]	80209	1		T1	1		T38	2		T31	15
valid_sources[0x14]	109145	1		T31	12		T6	441		T45	99
valid_sources[0x15]	81063	1		T1	2		T29	1		T31	10
valid_sources[0x16]	79315	1		T1	1		T31	13		T6	353
valid_sources[0x17]	173879	1		T1	1		T31	3		T6	424
valid_sources[0x18]	112699	1		T31	11		T34	3		T6	397
valid_sources[0x19]	119221	1		T31	10		T6	425		T45	108
valid_sources[0x1a]	291602	1		T1	1		T31	4		T6	429
valid_sources[0x1b]	80140	1		T31	9		T6	428		T45	102
valid_sources[0x1c]	80890	1		T31	12		T6	439		T45	98
valid_sources[0x1d]	157264	1		T38	1		T31	14		T6	409
valid_sources[0x1e]	80713	1		T31	10		T33	1		T6	383
valid_sources[0x1f]	82838	1		T31	11		T6	441		T45	105
valid_sources[0x20]	81521	1		T1	3		T38	3		T31	24
valid_sources[0x21]	229410	1		T1	2		T31	11		T6	433
valid_sources[0x22]	80583	1		T1	1		T31	18		T6	407
valid_sources[0x23]	81071	1		T31	17		T6	415		T45	96
valid_sources[0x24]	80799	1		T1	2		T31	20		T6	392
valid_sources[0x25]	225679	1		T1	3		T38	1		T31	11
valid_sources[0x26]	98167	1		T31	21		T6	414		T45	116
valid_sources[0x27]	81241	1		T1	3		T31	10		T6	419
valid_sources[0x28]	83150	1		T31	12		T6	410		T112	1
valid_sources[0x29]	82091	1		T31	6		T6	426		T45	108
valid_sources[0x2a]	289041	1		T1	2		T31	18		T6	384
valid_sources[0x2b]	658011	1		T1	1		T31	25		T6	386
valid_sources[0x2c]	186637	1		T31	14		T6	405		T112	1
valid_sources[0x2d]	80492	1		T31	14		T33	1		T6	432
valid_sources[0x2e]	80652	1		T31	17		T6	432		T45	132
valid_sources[0x2f]	79983	1		T31	16		T6	400		T45	114
valid_sources[0x30]	79386	1		T31	18		T6	423		T45	119
valid_sources[0x31]	583461	1		T31	16		T6	398		T45	118
valid_sources[0x32]	80568	1		T1	2		T31	23		T6	413
valid_sources[0x33]	148745	1		T31	18		T6	347		T45	97
valid_sources[0x34]	80949	1		T31	19		T6	423		T45	99
valid_sources[0x35]	84219	1		T1	4		T31	17		T33	1
valid_sources[0x36]	140431	1		T1	1		T31	13		T6	388
valid_sources[0x37]	195599	1		T1	2		T31	20		T5	111568
valid_sources[0x38]	104696	1		T1	1		T31	13		T6	377
valid_sources[0x39]	366869	1		T31	5		T6	417		T45	103
valid_sources[0x3a]	81033	1		T1	1		T31	18		T6	405
valid_sources[0x3b]	83087	1		T31	19		T6	445		T45	88
valid_sources[0x3c]	87347	1		T29	3		T38	2		T31	15
valid_sources[0x3d]	82664	1		T1	1		T31	20		T6	439
valid_sources[0x3e]	81666	1		T31	11		T6	412		T45	107
valid_sources[0x3f]	82383	1		T1	1		T31	19		T6	388
valid_sources[0x40]	82512	1		T1	1		T31	14		T6	423
valid_sources[0x41]	80158	1		T31	20		T6	360		T45	102
valid_sources[0x42]	80337	1		T1	2		T38	1		T31	15
valid_sources[0x43]	81410	1		T1	1		T31	9		T6	399
valid_sources[0x44]	190307	1		T38	1		T31	7		T6	444
valid_sources[0x45]	82205	1		T31	14		T6	452		T45	93
valid_sources[0x46]	82200	1		T31	22		T6	411		T45	111
valid_sources[0x47]	78432	1		T31	11		T6	391		T45	111
valid_sources[0x48]	80734	1		T31	13		T6	414		T112	1
valid_sources[0x49]	79733	1		T1	1		T38	1		T31	12
valid_sources[0x4a]	149177	1		T1	2		T31	15		T6	438
valid_sources[0x4b]	81818	1		T31	10		T6	439		T45	110
valid_sources[0x4c]	95056	1		T31	12		T6	406		T45	117
valid_sources[0x4d]	139732	1		T4	57799		T31	23		T33	1
valid_sources[0x4e]	80525	1		T1	1		T31	14		T6	386
valid_sources[0x4f]	80730	1		T1	2		T31	15		T6	438
valid_sources[0x50]	79942	1		T1	1		T31	10		T6	405
valid_sources[0x51]	81672	1		T1	1		T31	17		T6	409
valid_sources[0x52]	81613	1		T1	1		T31	9		T6	390
valid_sources[0x53]	86655	1		T1	1		T31	23		T6	430
valid_sources[0x54]	79901	1		T1	2		T31	18		T6	392
valid_sources[0x55]	83527	1		T31	3		T6	379		T45	104
valid_sources[0x56]	234851	1		T1	1		T31	8		T6	419
valid_sources[0x57]	80562	1		T31	15		T6	377		T45	110
valid_sources[0x58]	84938	1		T1	1		T31	22		T6	411
valid_sources[0x59]	82068	1		T1	3		T2	2		T38	1
valid_sources[0x5a]	157587	1		T1	1		T31	9		T6	391
valid_sources[0x5b]	79097	1		T1	1		T31	13		T6	415
valid_sources[0x5c]	82520	1		T1	2		T2	2		T31	23
valid_sources[0x5d]	81382	1		T38	3		T31	14		T6	411
valid_sources[0x5e]	83548	1		T38	1		T31	14		T6	409
valid_sources[0x5f]	83168	1		T1	3		T31	21		T6	388
valid_sources[0x60]	81071	1		T1	1		T38	3		T31	22
valid_sources[0x61]	108747	1		T31	15		T6	385		T45	100
valid_sources[0x62]	106278	1		T1	1		T31	19		T6	401
valid_sources[0x63]	394752	1		T1	1		T29	2		T31	17
valid_sources[0x64]	81788	1		T1	1		T38	1		T31	20
valid_sources[0x65]	82238	1		T1	2		T31	12		T6	360
valid_sources[0x66]	184727	1		T1	1		T31	17		T6	432
valid_sources[0x67]	82505	1		T31	12		T6	358		T45	82
valid_sources[0x68]	79296	1		T1	1		T31	15		T6	410
valid_sources[0x69]	82906	1		T1	1		T31	14		T6	372
valid_sources[0x6a]	114049	1		T31	11		T6	393		T45	103
valid_sources[0x6b]	104489	1		T31	10		T33	1		T6	416
valid_sources[0x6c]	395802	1		T1	2		T31	16		T6	386
valid_sources[0x6d]	82683	1		T1	1		T31	13		T6	364
valid_sources[0x6e]	120554	1		T1	3		T31	13		T6	408
valid_sources[0x6f]	113538	1		T1	1		T31	15		T6	382
valid_sources[0x70]	83092	1		T1	3		T38	2		T31	19
valid_sources[0x71]	106879	1		T31	6		T6	378		T37	2
valid_sources[0x72]	105011	1		T2	4		T31	8		T6	434
valid_sources[0x73]	80474	1		T1	1		T28	13		T31	8
valid_sources[0x74]	80955	1		T1	1		T31	9		T6	401
valid_sources[0x75]	126228	1		T1	1		T31	7		T6	439
valid_sources[0x76]	82281	1		T1	2		T31	18		T33	1
valid_sources[0x77]	81897	1		T31	20		T6	425		T37	1
valid_sources[0x78]	80995	1		T1	1		T31	21		T6	473
valid_sources[0x79]	80087	1		T38	5		T31	26		T6	376
valid_sources[0x7a]	82472	1		T1	2		T31	21		T6	375
valid_sources[0x7b]	81208	1		T1	3		T31	34		T6	413
valid_sources[0x7c]	79465	1		T1	1		T31	17		T6	410
valid_sources[0x7d]	254560	1		T31	23		T6	419		T45	102
valid_sources[0x7e]	80967	1		T1	1		T31	10		T6	435
valid_sources[0x7f]	82211	1		T31	15		T6	430		T45	93
valid_sources[0x80]	152225	1		T1	2		T31	11		T6	435

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15151271

1

T1

107

T2

2

T3

7

values[0x0]

all_enables

biggest_size

191542

1

T1

32

T2

1

T3

4

values[0x1]

all_enables

biggest_size

177327

1

T1

12

T2

2

T3

2