Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14871528	1		T1	76		T2	6		T3	5
full_word	15521041	1		T1	151		T2	5		T3	13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30392309	1		T1	227		T2	11		T3	18
auto[TlIntgErrCmd]	90	1		T212	2		T237	3		T244	3
auto[TlIntgErrData]	71	1		T212	2		T237	6		T244	1
auto[TlIntgErrBoth]	99	1		T212	6		T237	1		T244	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29891739	1		T1	150		T2	4		T3	9
auto[1]	500830	1		T1	77		T2	7		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14740225	1		T1	43		T2	2		T3	2
auto[TlIntgErrNone]	partial	auto[1]	131064	1		T1	33		T2	4		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	15151416	1		T1	107		T2	2		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	369604	1		T1	44		T2	3		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T237	1		T307	2		T308	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T212	1		T237	2		T244	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T309	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T212	1		T307	2		T308	1
auto[TlIntgErrData]	partial	auto[0]	28	1		T212	1		T237	1		T244	1
auto[TlIntgErrData]	partial	auto[1]	38	1		T212	1		T237	5		T307	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T254	1		T314	1		T315	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T308	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T212	1		T237	1		T244	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1		T212	5		T244	5		T307	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T307	1		T309	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T308	1		T316	1		T317	2