Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	489151700	11001	0	0
ep_in_enable_rd_A	489151700	1941	0	0
ep_out_enable_rd_A	489151700	2200	0	0
in_iso_rd_A	489151700	2147	0	0
intr_enable_rd_A	489151700	3254	0	0
out_iso_rd_A	489151700	2536	0	0
phy_config_rd_A	489151700	1535	0	0
phy_pins_drive_rd_A	489151700	1993	0	0
rxenable_setup_rd_A	489151700	2119	0	0
set_nak_out_rd_A	489151700	1999	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	11001	0	0
T210	7617	283	0	0
T211	10568	26	0	0
T212	19418	3	0	0
T236	9903	19	0	0
T243	9896	420	0	0
T245	6314	433	0	0
T248	3370	336	0	0
T249	7681	1014	0	0
T253	8581	16	0	0
T257	7992	15	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	1941	0	0
T211	10568	36	0	0
T212	19418	281	0	0
T214	7433	36	0	0
T274	3340	2	0	0
T275	4104	4	0	0
T282	4312	2	0	0
T286	2442	4	0	0
T287	44587	231	0	0
T288	8213	11	0	0
T289	40285	351	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	2200	0	0
T211	10568	19	0	0
T212	19418	207	0	0
T214	7433	14	0	0
T274	3340	3	0	0
T275	4104	55	0	0
T282	4312	12	0	0
T286	2442	1	0	0
T287	44587	216	0	0
T288	8213	71	0	0
T289	40285	505	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	2147	0	0
T211	10568	7	0	0
T212	19418	342	0	0
T214	7433	2	0	0
T274	3340	1	0	0
T275	4104	38	0	0
T282	4312	19	0	0
T286	2442	43	0	0
T287	44587	225	0	0
T288	8213	13	0	0
T289	40285	492	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	3254	0	0
T211	10568	57	0	0
T212	19418	264	0	0
T214	7433	31	0	0
T219	1771	13	0	0
T220	2932	11	0	0
T250	13607	3	0	0
T287	44587	243	0	0
T290	3223	26	0	0
T291	5306	7	0	0
T292	1823	10	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	2536	0	0
T211	10568	42	0	0
T212	19418	392	0	0
T214	7433	9	0	0
T274	3340	4	0	0
T275	4104	64	0	0
T282	4312	21	0	0
T286	2442	7	0	0
T287	44587	211	0	0
T288	8213	8	0	0
T289	40285	650	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	1535	0	0
T211	10568	16	0	0
T212	19418	152	0	0
T214	7433	46	0	0
T274	3340	7	0	0
T275	4104	38	0	0
T282	4312	18	0	0
T286	2442	1	0	0
T287	44587	186	0	0
T288	8213	51	0	0
T289	40285	197	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	1993	0	0
T211	10568	41	0	0
T212	19418	113	0	0
T214	7433	30	0	0
T274	3340	3	0	0
T275	4104	27	0	0
T282	4312	20	0	0
T286	2442	34	0	0
T287	44587	195	0	0
T288	8213	11	0	0
T289	40285	600	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	2119	0	0
T211	10568	16	0	0
T212	19418	370	0	0
T214	7433	37	0	0
T275	4104	12	0	0
T282	4312	13	0	0
T286	2442	5	0	0
T287	44587	206	0	0
T288	8213	58	0	0
T289	40285	571	0	0
T293	3410	40	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489151700	1999	0	0
T211	10568	10	0	0
T212	19418	340	0	0
T214	7433	18	0	0
T274	3340	2	0	0
T275	4104	9	0	0
T282	4312	19	0	0
T286	2442	4	0	0
T287	44587	183	0	0
T288	8213	23	0	0
T289	40285	460	0	0