Unified Coverage Report :: Module :: usbdev_linkstate

Module : usbdev_linkstate

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.84	90.38	89.86		70.37	78.57	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usbdev_linkstate	85.84	90.38	89.86		70.37	78.57	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usbdev_linkstate

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.84	90.38	89.86		70.37	78.57	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.34	92.19	91.76		70.37	82.35	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.01	98.89	97.59			95.56	100.00	usbdev_impl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
filter_pwr_sense	100.00	100.00	100.00			100.00
filter_se0	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_linkstate

	Line No.	Total	Covered	Percent
TOTAL		104	94	90.38
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	34	24	70.59
ALWAYS	231	3	3	100.00
ALWAYS	245	18	18	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	292	5	5	100.00
ALWAYS	307	16	16	100.00
ALWAYS	348	5	5	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	367	6	6	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	380	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
92	1	1
93	1	1
94	1	1
96	1	1
99	1	1
105	1	1
133	1	1
135	1	1
139	1	1
140	1	1
144	1	1
145	1	1
147	1	1
150	1	1
151	1	1
			==> MISSING_ELSE
156	1	1
157	1	1
158	1	1
161	1	1
162	1	1
163	0	1
			MISSING_ELSE
168	0	1
169	0	1
170	0	1
171	0	1
172	0	1
			==> MISSING_ELSE
184	1	1
185	1	1
186	1	1
			MISSING_ELSE
195	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
204	1	1
205	0	1
206	1	1
207	0	1
			MISSING_ELSE
212	1	1
213	0	1
214	0	1
215	1	1
216	1	1
			MISSING_ELSE
231	1	1
232	1	1
234	1	1
245	1	1
246	1	1
247	1	1
248	1	1
250	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
261	1	1
262	1	1
264	1	1
265	1	1
266	1	1
268	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
280	1	1
289	1	1
292	1	1
293	1	1
294	1	1
296	1	1
297	1	1
307	1	1
308	1	1
309	1	1
311	1	1
314	1	1
315	1	1
316	1	1
			MISSING_ELSE
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
329	1	1
			MISSING_ELSE
336	1	1
337	1	1
			==> MISSING_ELSE
348	1	1
349	1	1
350	1	1
352	1	1
353	1	1
365	1	1
367	1	1
368	1	1
370	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
380	1	1
381	1	1
383	1	1
384	1	1
385	1	1
386	1	1
			MISSING_ELSE

---

Cond Coverage for Module : usbdev_linkstate

	Total	Covered	Percent
Conditions	69	62	89.86
Logical	69	62	89.86
Non-Logical	0	0
Event	0	0

 LINE       92
 EXPRESSION (link_state_q == LinkDisconnected)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       94
 EXPRESSION ((link_state_q == LinkSuspended) || (link_state_q == LinkPoweredSuspended))
             ---------------1---------------    -------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T17,T8

 LINE       94
 SUB-EXPRESSION (link_state_q == LinkSuspended)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T17,T8

 LINE       94
 SUB-EXPRESSION (link_state_q == LinkPoweredSuspended)
                -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       96
 EXPRESSION ((link_state_q == LinkActive) || (link_state_q == LinkActiveNoSOF))
             --------------1-------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T43,T44

 LINE       96
 SUB-EXPRESSION (link_state_q == LinkActive)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T36,T43,T44

 LINE       96
 SUB-EXPRESSION (link_state_q == LinkActiveNoSOF)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 EXPRESSION ((usb_dn_i == 1'b0) & (usb_dp_i == 1'b0) & (usb_oe_i == 1'b0))
             ---------1--------   ---------2--------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T4,T28
1	1	1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (usb_dn_i == 1'b0)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (usb_dp_i == 1'b0)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (usb_oe_i == 1'b0)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (see_pwr_sense ? ((link_state_q == LinkPowered) | link_active_o) : 1'b0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION ((link_state_q == LinkPowered) | link_active_o)
                 --------------1--------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (link_state_q == LinkPowered)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (((!see_pwr_sense)) || ((!usb_pullup_en_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T45,T46
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (see_pwr_sense & usb_pullup_en_i)
             ------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       184
 EXPRESSION (rx_j_det_i | ev_reset)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T17,T8
0	1	Not Covered
1	0	Covered	T7,T17,T8

 LINE       265
 EXPRESSION (link_rst_timer_q == RESET_TIMEOUT)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       315
 EXPRESSION (((!ev_bus_active)) && monitor_inac)
             ---------1--------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T17,T8
1	1	Covered	T1,T2,T3

 LINE       322
 EXPRESSION (ev_bus_active || ((!monitor_inac)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       325
 EXPRESSION (link_inac_timer_q == SUSPEND_TIMEOUT)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T17,T8

 LINE       336
 EXPRESSION (ev_bus_active || ((!monitor_inac)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T7,T17,T8
1	0	Not Covered

 LINE       370
 EXPRESSION (sof_detected_i || ((!link_active_o)) || link_reset)
             -------1------    ---------2--------    -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T29,T8,T21
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T36,T43,T44

 LINE       372
 EXPRESSION (sof_missed_o && ((!host_lost_o)))
             ------1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T31,T45
1	1	Covered	T4,T31,T5

 LINE       378
 EXPRESSION (missing_sof_timer == SOF_TIMEOUT)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T31,T5

 LINE       383
 EXPRESSION (sof_missed_o || sof_detected_i || ((!link_active_o)) || link_reset)
             ------1-----    -------2------    ---------3--------    -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T29,T8,T21
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Covered	T36,T43,T44
1	0	0	0	Covered	T4,T31,T5

---

FSM Coverage for Module : usbdev_linkstate

Summary for FSM :: link_state_q

	Total	Covered	Percent
States	7	6	85.71	(Not included in score)
Transitions	19	11	57.89
Sequences	0	0

State, Transition and Sequence Details for FSM :: link_state_q

---

states	Line No.	Covered	Tests
LinkActive	198	Covered	T36,T43,T44
LinkActiveNoSOF	157	Covered	T1,T2,T3
LinkDisconnected	145	Covered	T1,T2,T3
LinkPowered	151	Covered	T1,T2,T3
LinkPoweredSuspended	163	Not Covered
LinkResuming	161	Covered	T7,T17,T8
LinkSuspended	196	Covered	T7,T17,T8

transitions	Line No.	Covered	Tests
LinkActive->LinkActiveNoSOF	207	Not Covered
LinkActive->LinkDisconnected	145	Covered	T43,T47,T48
LinkActive->LinkSuspended	205	Not Covered
LinkActiveNoSOF->LinkActive	198	Covered	T36,T43,T44
LinkActiveNoSOF->LinkDisconnected	145	Covered	T7,T8,T9
LinkActiveNoSOF->LinkSuspended	196	Covered	T7,T17,T8
LinkDisconnected->LinkPowered	151	Covered	T1,T2,T3
LinkPowered->LinkActiveNoSOF	157	Covered	T1,T2,T3
LinkPowered->LinkDisconnected	145	Covered	T14,T49,T50
LinkPowered->LinkPoweredSuspended	163	Not Covered
LinkPowered->LinkResuming	161	Covered	T51
LinkPoweredSuspended->LinkActiveNoSOF	169	Not Covered
LinkPoweredSuspended->LinkDisconnected	145	Not Covered
LinkPoweredSuspended->LinkPowered	172	Not Covered
LinkResuming->LinkActiveNoSOF	186	Covered	T7,T17,T8
LinkResuming->LinkDisconnected	145	Not Covered
LinkSuspended->LinkActiveNoSOF	214	Not Covered
LinkSuspended->LinkDisconnected	145	Covered	T10,T12,T14
LinkSuspended->LinkResuming	216	Covered	T7,T17,T8

Summary for FSM :: link_rst_state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: link_rst_state_q

---

states	Line No.	Covered	Tests
NoRst	262	Covered	T1,T2,T3
RstCnt	254	Covered	T1,T2,T3
RstPend	266	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
NoRst->RstCnt	254	Covered	T1,T2,T3
RstCnt->NoRst	262	Covered	T1,T2,T3
RstCnt->RstPend	266	Covered	T1,T2,T3
RstPend->NoRst	277	Covered	T1,T2,T3

Summary for FSM :: link_inac_state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: link_inac_state_q

---

states	Line No.	Covered	Tests
Active	323	Covered	T1,T2,T3
InactCnt	316	Covered	T1,T2,T3
InactPend	326	Covered	T7,T17,T8

transitions	Line No.	Covered	Tests
Active->InactCnt	316	Covered	T1,T2,T3
InactCnt->Active	323	Covered	T1,T2,T3
InactCnt->InactPend	326	Covered	T7,T17,T8
InactPend->Active	337	Covered	T7,T17,T8

---

Branch Coverage for Module : usbdev_linkstate

	Line No.	Total	Covered	Percent
Branches		56	44	78.57
TERNARY	135	2	2	100.00
IF	144	22	13	59.09
IF	231	2	2	100.00
CASE	250	9	8	88.89
IF	292	2	2	100.00
CASE	311	9	7	77.78
IF	348	2	2	100.00
IF	367	4	4	100.00
IF	380	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	135	(see_pwr_sense) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	144	if (((!see_pwr_sense) || (!usb_pullup_en_i)))
-2-:	147	case (link_state_q)
-3-:	150	if ((see_pwr_sense & usb_pullup_en_i))
-4-:	156	if (ev_reset)
-5-:	158	if (resume_link_active_i)
-6-:	162	if (ev_bus_inactive)
-7-:	168	if (ev_reset)
-8-:	170	if (ev_bus_active)
-9-:	184	if ((rx_j_det_i | ev_reset))
-10-:	195	if (ev_bus_inactive)
-11-:	197	if (sof_detected_i)
-12-:	204	if (ev_bus_inactive)
-13-:	206	if (ev_reset)
-14-:	212	if (ev_reset)
-15-:	215	if (ev_bus_active)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkDisconnected	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkDisconnected	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
0	LinkPowered	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkPowered	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T51
0	LinkPowered	-	0	0	1	-	-	-	-	-	-	-	-	-	Not Covered
0	LinkPowered	-	0	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkPoweredSuspended	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
0	LinkPoweredSuspended	-	-	-	-	0	1	-	-	-	-	-	-	-	Not Covered
0	LinkPoweredSuspended	-	-	-	-	0	0	-	-	-	-	-	-	-	Not Covered
0	LinkResuming	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T17,T8
0	LinkResuming	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T7,T17,T8
0	LinkActiveNoSOF	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T7,T17,T8
0	LinkActiveNoSOF	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T36,T43,T44
0	LinkActiveNoSOF	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T1,T2,T3
0	LinkActive	-	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
0	LinkActive	-	-	-	-	-	-	-	-	-	0	1	-	-	Not Covered
0	LinkActive	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T36,T43,T44
0	LinkSuspended	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
0	LinkSuspended	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T7,T17,T8
0	LinkSuspended	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T7,T17,T8
0	default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	case (link_rst_state_q)
-2-:	253	if (see_se0)
-3-:	261	if ((!see_se0))
-4-:	264	if (us_tick_i)
-5-:	265	if ((link_rst_timer_q == RESET_TIMEOUT))
-6-:	276	if ((!see_se0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
NoRst	1	-	-	-	-	Covered	T1,T2,T3
NoRst	0	-	-	-	-	Covered	T1,T2,T3
RstCnt	-	1	-	-	-	Covered	T1,T2,T3
RstCnt	-	0	1	1	-	Covered	T1,T2,T3
RstCnt	-	0	1	0	-	Covered	T1,T2,T3
RstCnt	-	0	0	-	-	Covered	T1,T2,T3
RstPend	-	-	-	-	1	Covered	T1,T2,T3
RstPend	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	case (link_inac_state_q)
-2-:	315	if (((!ev_bus_active) && monitor_inac))
-3-:	322	if ((ev_bus_active || (!monitor_inac)))
-4-:	324	if (us_tick_i)
-5-:	325	if ((link_inac_timer_q == SUSPEND_TIMEOUT))
-6-:	336	if ((ev_bus_active || (!monitor_inac)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
Active	1	-	-	-	-	Covered	T1,T2,T3
Active	0	-	-	-	-	Covered	T1,T2,T3
InactCnt	-	1	-	-	-	Covered	T1,T2,T3
InactCnt	-	0	1	1	-	Covered	T7,T17,T8
InactCnt	-	0	1	0	-	Covered	T1,T2,T3
InactCnt	-	0	0	-	-	Covered	T1,T2,T3
InactPend	-	-	-	-	1	Covered	T7,T17,T8
InactPend	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	348	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	367	if ((!rst_ni))
-2-:	370	if (((sof_detected_i || (!link_active_o)) || link_reset))
-3-:	372	if ((sof_missed_o && (!host_lost_o)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T31,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	380	if ((!rst_ni))
-2-:	383	if ((((sof_missed_o || sof_detected_i) || (!link_active_o)) || link_reset))
-3-:	385	if (us_tick_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_linkstate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
LincInacStateValid_A	487480219	487276602	0	0
LinkRstStateValid_A	487480219	487276602	0	0
LinkStateValid_A	487480219	487276602	0	0

LincInacStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487480219	487276602	0	0
T1	43654	43561	0	0
T2	7381	7320	0	0
T3	7822	7760	0	0
T4	426650	426580	0	0
T28	13402	13305	0	0
T29	9847	9772	0	0
T30	8581	8496	0	0
T31	319581	319512	0	0
T32	7723	7630	0	0
T38	16540	16483	0	0

LinkRstStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487480219	487276602	0	0
T1	43654	43561	0	0
T2	7381	7320	0	0
T3	7822	7760	0	0
T4	426650	426580	0	0
T28	13402	13305	0	0
T29	9847	9772	0	0
T30	8581	8496	0	0
T31	319581	319512	0	0
T32	7723	7630	0	0
T38	16540	16483	0	0

LinkStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487480219	487276602	0	0
T1	43654	43561	0	0
T2	7381	7320	0	0
T3	7822	7760	0	0
T4	426650	426580	0	0
T28	13402	13305	0	0
T29	9847	9772	0	0
T30	8581	8496	0	0
T31	319581	319512	0	0
T32	7723	7630	0	0
T38	16540	16483	0	0