Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14722296	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15336071	1		T1	6		T2	7		T3	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29572448	1		T1	3		T2	3		T3	3
values[0x0]	242804	1		T1	3		T2	5		T3	5
values[0x1]	243115	1		T1	6		T2	4		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11737291	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18321076	1		T1	9		T2	9		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	199304	1		T17	4		T4	348		T6	149
valid_sources[0x01]	86218	1		T4	319		T6	201		T161	380
valid_sources[0x02]	88417	1		T28	3		T17	1		T4	286
valid_sources[0x03]	85481	1		T4	339		T6	160		T161	266
valid_sources[0x04]	162111	1		T7	7		T17	1		T4	321
valid_sources[0x05]	86254	1		T4	351		T23	1		T6	139
valid_sources[0x06]	87719	1		T17	2		T4	272		T103	1
valid_sources[0x07]	86702	1		T30	2		T4	262		T6	160
valid_sources[0x08]	195516	1		T28	1		T17	1		T4	360
valid_sources[0x09]	87895	1		T28	1		T4	343		T23	1
valid_sources[0x0a]	85759	1		T4	342		T23	1		T47	1
valid_sources[0x0b]	172230	1		T28	4		T17	2		T4	372
valid_sources[0x0c]	102077	1		T4	262		T103	1		T6	156
valid_sources[0x0d]	86149	1		T2	4		T4	302		T6	171
valid_sources[0x0e]	86869	1		T30	1		T17	1		T8	4
valid_sources[0x0f]	92284	1		T28	1		T17	1		T4	354
valid_sources[0x10]	202151	1		T28	9		T17	1		T4	355
valid_sources[0x11]	86823	1		T8	1		T4	375		T20	1
valid_sources[0x12]	86606	1		T17	1		T4	330		T20	5
valid_sources[0x13]	89151	1		T17	1		T8	5		T4	309
valid_sources[0x14]	164572	1		T28	5		T17	1		T4	345
valid_sources[0x15]	86445	1		T17	1		T8	1		T4	330
valid_sources[0x16]	120323	1		T17	2		T8	1		T4	433
valid_sources[0x17]	86261	1		T8	1		T4	366		T6	162
valid_sources[0x18]	212361	1		T28	3		T8	2		T4	292
valid_sources[0x19]	207479	1		T7	10		T17	1		T4	299
valid_sources[0x1a]	104196	1		T30	1		T17	2		T4	333
valid_sources[0x1b]	87191	1		T17	2		T4	298		T6	192
valid_sources[0x1c]	86402	1		T28	1		T7	7		T17	1
valid_sources[0x1d]	89231	1		T28	1		T17	1		T4	328
valid_sources[0x1e]	408552	1		T17	1		T4	298		T6	202
valid_sources[0x1f]	87420	1		T28	1		T17	1		T8	2
valid_sources[0x20]	85636	1		T8	1		T4	374		T6	147
valid_sources[0x21]	88110	1		T7	1		T17	2		T8	2
valid_sources[0x22]	87688	1		T28	1		T17	3		T4	302
valid_sources[0x23]	86894	1		T7	1		T8	1		T4	281
valid_sources[0x24]	87126	1		T28	2		T17	1		T4	274
valid_sources[0x25]	86625	1		T28	8		T17	2		T8	2
valid_sources[0x26]	86168	1		T8	3		T4	318		T6	165
valid_sources[0x27]	85741	1		T28	2		T17	1		T4	318
valid_sources[0x28]	86955	1		T4	270		T6	163		T161	301
valid_sources[0x29]	86363	1		T4	419		T23	1		T6	193
valid_sources[0x2a]	206069	1		T29	13		T8	3		T4	345
valid_sources[0x2b]	86322	1		T28	5		T17	1		T4	341
valid_sources[0x2c]	237325	1		T17	1		T4	331		T5	38686
valid_sources[0x2d]	87793	1		T17	1		T8	2		T4	320
valid_sources[0x2e]	86699	1		T17	1		T4	356		T6	160
valid_sources[0x2f]	86943	1		T28	4		T4	348		T6	182
valid_sources[0x30]	87816	1		T17	2		T8	1		T4	390
valid_sources[0x31]	88491	1		T28	7		T17	1		T4	280
valid_sources[0x32]	185192	1		T28	4		T4	278		T6	165
valid_sources[0x33]	121212	1		T7	2		T4	388		T6	141
valid_sources[0x34]	87254	1		T8	2		T4	349		T6	143
valid_sources[0x35]	91490	1		T28	2		T17	1		T4	324
valid_sources[0x36]	357428	1		T2	1		T28	1		T30	1
valid_sources[0x37]	105634	1		T17	1		T4	321		T23	1
valid_sources[0x38]	89217	1		T28	1		T8	3		T4	338
valid_sources[0x39]	87408	1		T4	418		T6	187		T161	270
valid_sources[0x3a]	151570	1		T4	326		T6	153		T161	248
valid_sources[0x3b]	275359	1		T17	2		T4	344		T6	160
valid_sources[0x3c]	89515	1		T28	2		T17	1		T4	413
valid_sources[0x3d]	87888	1		T4	362		T6	175		T161	289
valid_sources[0x3e]	87765	1		T7	4		T17	1		T4	298
valid_sources[0x3f]	87375	1		T28	5		T4	300		T6	186
valid_sources[0x40]	86909	1		T28	1		T17	2		T4	295
valid_sources[0x41]	151603	1		T17	2		T4	340		T6	169
valid_sources[0x42]	85204	1		T28	4		T4	285		T20	1
valid_sources[0x43]	86382	1		T18	189		T4	392		T23	2
valid_sources[0x44]	170779	1		T28	4		T17	2		T4	319
valid_sources[0x45]	87509	1		T28	1		T17	2		T4	403
valid_sources[0x46]	220444	1		T4	305		T6	166		T161	326
valid_sources[0x47]	88855	1		T28	3		T4	307		T6	195
valid_sources[0x48]	86460	1		T4	319		T20	1		T23	1
valid_sources[0x49]	131712	1		T17	1		T4	342		T103	1
valid_sources[0x4a]	270518	1		T27	4		T4	292		T6	163
valid_sources[0x4b]	86052	1		T4	326		T6	180		T161	259
valid_sources[0x4c]	86970	1		T17	2		T4	324		T6	178
valid_sources[0x4d]	86364	1		T28	2		T17	1		T4	248
valid_sources[0x4e]	86152	1		T28	2		T7	1		T4	339
valid_sources[0x4f]	204139	1		T27	3		T4	323		T20	1
valid_sources[0x50]	89133	1		T28	1		T4	335		T20	1
valid_sources[0x51]	92040	1		T28	1		T7	3		T17	1
valid_sources[0x52]	86395	1		T28	1		T30	1		T7	2
valid_sources[0x53]	87501	1		T4	363		T6	162		T161	309
valid_sources[0x54]	111931	1		T7	2		T17	1		T4	346
valid_sources[0x55]	85380	1		T2	1		T17	1		T8	2
valid_sources[0x56]	88795	1		T17	1		T4	341		T23	1
valid_sources[0x57]	88736	1		T27	3		T30	1		T17	3
valid_sources[0x58]	86734	1		T28	6		T30	1		T17	1
valid_sources[0x59]	85779	1		T28	3		T17	2		T4	295
valid_sources[0x5a]	177128	1		T28	1		T17	1		T4	326
valid_sources[0x5b]	87693	1		T3	4		T17	1		T4	368
valid_sources[0x5c]	86602	1		T2	2		T17	1		T4	309
valid_sources[0x5d]	87938	1		T4	346		T23	1		T47	2
valid_sources[0x5e]	301399	1		T28	3		T17	2		T4	356
valid_sources[0x5f]	88735	1		T17	1		T8	6		T4	322
valid_sources[0x60]	128722	1		T8	1		T4	295		T6	190
valid_sources[0x61]	86913	1		T7	2		T17	1		T8	1
valid_sources[0x62]	86762	1		T28	3		T17	1		T4	372
valid_sources[0x63]	112196	1		T8	3		T4	371		T6	190
valid_sources[0x64]	86884	1		T17	1		T8	3		T4	326
valid_sources[0x65]	87343	1		T28	3		T30	2		T17	1
valid_sources[0x66]	87532	1		T2	1		T28	2		T17	2
valid_sources[0x67]	86392	1		T28	1		T17	1		T4	315
valid_sources[0x68]	86447	1		T8	2		T4	380		T23	1
valid_sources[0x69]	86406	1		T4	322		T20	1		T6	165
valid_sources[0x6a]	86377	1		T28	1		T17	1		T8	3
valid_sources[0x6b]	178706	1		T4	319		T6	209		T161	280
valid_sources[0x6c]	86761	1		T28	3		T17	1		T4	312
valid_sources[0x6d]	116955	1		T28	2		T30	1		T8	1
valid_sources[0x6e]	86687	1		T28	2		T17	1		T4	332
valid_sources[0x6f]	87276	1		T4	295		T6	172		T161	291
valid_sources[0x70]	87207	1		T27	5		T8	3		T4	295
valid_sources[0x71]	116134	1		T28	4		T4	323		T6	174
valid_sources[0x72]	219811	1		T17	1		T4	273		T6	156
valid_sources[0x73]	89845	1		T7	12		T17	2		T4	328
valid_sources[0x74]	129015	1		T28	8		T30	1		T17	1
valid_sources[0x75]	89066	1		T28	2		T4	349		T47	1
valid_sources[0x76]	127211	1		T17	2		T8	2		T4	356
valid_sources[0x77]	87647	1		T27	5		T28	3		T17	3
valid_sources[0x78]	236572	1		T28	7		T7	2		T8	1
valid_sources[0x79]	270676	1		T8	1		T4	304		T6	160
valid_sources[0x7a]	87302	1		T2	1		T7	9		T17	2
valid_sources[0x7b]	438520	1		T28	2		T4	301		T20	1
valid_sources[0x7c]	85523	1		T28	1		T17	1		T4	310
valid_sources[0x7d]	93294	1		T17	3		T4	380		T20	1
valid_sources[0x7e]	86387	1		T28	3		T17	2		T8	1
valid_sources[0x7f]	86094	1		T28	1		T30	1		T17	1
valid_sources[0x80]	86190	1		T17	2		T8	1		T4	351

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14971533

1

T1

1

T3

1

T27

9

values[0x0]

all_enables

biggest_size

189933

1

T1

2

T2

5

T3

4

values[0x1]

all_enables

biggest_size

174605

1

T1

3

T2

2

T3

2