Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14737657	1		T1	6		T2	5		T3	5
full_word	15337199	1		T1	6		T2	7		T3	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30074586	1		T1	12		T2	12		T3	12
auto[TlIntgErrCmd]	90	1		T225	8		T227	5		T247	2
auto[TlIntgErrData]	82	1		T225	4		T227	6		T247	1
auto[TlIntgErrBoth]	98	1		T225	8		T227	9		T247	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29574516	1		T1	3		T2	3		T3	3
auto[1]	500340	1		T1	9		T2	9		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14602665	1		T1	2		T2	3		T3	2
auto[TlIntgErrNone]	partial	auto[1]	134744	1		T1	4		T2	2		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	14971718	1		T1	1		T3	1		T27	9
auto[TlIntgErrNone]	full_word	auto[1]	365459	1		T1	5		T2	7		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T225	3		T227	1		T266	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T225	5		T227	3		T247	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T338	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T227	1		T247	1		T266	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T225	1		T227	4		T247	1
auto[TlIntgErrData]	partial	auto[1]	32	1		T225	2		T227	2		T266	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T225	1		T267	1		T336	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T339	1		T338	3		T340	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1		T225	4		T227	6		T247	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T225	4		T227	3		T247	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T247	2		T337	1		T312	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T341	1		-	-		-	-