Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	483120171	12523	0	0
ep_in_enable_rd_A	483120171	1379	0	0
ep_out_enable_rd_A	483120171	1302	0	0
in_iso_rd_A	483120171	1565	0	0
intr_enable_rd_A	483120171	2173	0	0
out_iso_rd_A	483120171	1417	0	0
phy_config_rd_A	483120171	783	0	0
phy_pins_drive_rd_A	483120171	1081	0	0
rxenable_setup_rd_A	483120171	1461	0	0
set_nak_out_rd_A	483120171	1387	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	12523	0	0
T225	33941	3	0	0
T226	9627	8	0	0
T227	42183	5	0	0
T241	2808	12	0	0
T242	5513	948	0	0
T247	37884	2	0	0
T248	7946	549	0	0
T257	13242	561	0	0
T265	4934	9	0	0
T266	15390	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	1379	0	0
T257	13242	6	0	0
T265	4934	3	0	0
T282	3393	36	0	0
T298	9183	50	0	0
T310	14647	85	0	0
T311	107430	212	0	0
T312	43030	295	0	0
T313	4446	84	0	0
T314	22280	163	0	0
T315	9226	5	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	1302	0	0
T260	11184	5	0	0
T265	4934	8	0	0
T282	3393	53	0	0
T288	2841	3	0	0
T298	9183	26	0	0
T310	14647	59	0	0
T311	107430	225	0	0
T312	43030	282	0	0
T313	4446	45	0	0
T314	22280	145	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	1565	0	0
T257	13242	4	0	0
T265	4934	33	0	0
T282	3393	54	0	0
T298	9183	47	0	0
T310	14647	105	0	0
T311	107430	314	0	0
T312	43030	276	0	0
T313	4446	8	0	0
T314	22280	281	0	0
T315	9226	30	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	2173	0	0
T230	2337	21	0	0
T265	4934	42	0	0
T282	3393	73	0	0
T298	9183	71	0	0
T310	14647	94	0	0
T316	2206	11	0	0
T317	3343	12	0	0
T318	2191	19	0	0
T319	2699	26	0	0
T320	2240	25	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	1417	0	0
T282	3393	29	0	0
T294	7413	7	0	0
T298	9183	76	0	0
T310	14647	90	0	0
T311	107430	252	0	0
T312	43030	328	0	0
T313	4446	8	0	0
T314	22280	231	0	0
T315	9226	26	0	0
T321	9276	30	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	783	0	0
T282	3393	19	0	0
T288	2841	6	0	0
T294	7413	12	0	0
T298	9183	43	0	0
T310	14647	36	0	0
T311	107430	113	0	0
T312	43030	89	0	0
T313	4446	8	0	0
T314	22280	104	0	0
T315	9226	9	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	1081	0	0
T265	4934	28	0	0
T282	3393	2	0	0
T288	2841	4	0	0
T298	9183	23	0	0
T310	14647	3	0	0
T311	107430	117	0	0
T312	43030	220	0	0
T313	4446	8	0	0
T314	22280	219	0	0
T315	9226	52	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	1461	0	0
T265	4934	17	0	0
T282	3393	5	0	0
T288	2841	6	0	0
T298	9183	75	0	0
T310	14647	89	0	0
T311	107430	365	0	0
T312	43030	321	0	0
T313	4446	63	0	0
T314	22280	238	0	0
T315	9226	9	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	1387	0	0
T265	4934	24	0	0
T282	3393	1	0	0
T288	2841	5	0	0
T298	9183	31	0	0
T310	14647	45	0	0
T311	107430	233	0	0
T312	43030	273	0	0
T313	4446	67	0	0
T314	22280	276	0	0
T315	9226	24	0	0