Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	88.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	88.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T30,T4,T20

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T62,T86,T87
1	1	0	Not Covered
1	1	1	Covered	T30,T4,T20

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T30,T4,T20
1	1	0	Not Covered
1	1	1	Covered	T30,T4,T20

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T30,T4,T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481407153	145395082	0	0
DepthKnown_A	481407153	481203896	0	0
RvalidKnown_A	481407153	481203896	0	0
WreadyKnown_A	481407153	481203896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	481407153	145395082	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	145395082	0	0
T4	175766	169518	0	0
T5	0	407255	0	0
T6	0	312516	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	0	0	0
T18	34029	0	0	0
T19	11098	0	0	0
T20	11079	573	0	0
T21	11718	0	0	0
T22	10214	0	0	0
T23	0	587	0	0
T30	9208	575	0	0
T80	0	562	0	0
T82	0	561	0	0
T83	0	10605	0	0
T84	0	593	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	145395082	0	0
T4	175766	169518	0	0
T5	0	407255	0	0
T6	0	312516	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	0	0	0
T18	34029	0	0	0
T19	11098	0	0	0
T20	11079	573	0	0
T21	11718	0	0	0
T22	10214	0	0	0
T23	0	587	0	0
T30	9208	575	0	0
T80	0	562	0	0
T82	0	561	0	0
T83	0	10605	0	0
T84	0	593	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T61,T63
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481407153	281622149	0	0
DepthKnown_A	481407153	481203896	0	0
RvalidKnown_A	481407153	481203896	0	0
WreadyKnown_A	481407153	481203896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	481407153	281622149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	281622149	0	0
T1	11575	2371	0	0
T2	11715	2371	0	0
T3	8559	299	0	0
T7	640056	785	0	0
T8	182133	1303	0	0
T17	42574	13485	0	0
T27	9285	1218	0	0
T28	49260	41204	0	0
T29	11489	1209	0	0
T30	9208	374	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	281622149	0	0
T1	11575	2371	0	0
T2	11715	2371	0	0
T3	8559	299	0	0
T7	640056	785	0	0
T8	182133	1303	0	0
T17	42574	13485	0	0
T27	9285	1218	0	0
T28	49260	41204	0	0
T29	11489	1209	0	0
T30	9208	374	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T50,T51,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T27,T28,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481407153	23714096	0	0
DepthKnown_A	481407153	481203896	0	0
RvalidKnown_A	481407153	481203896	0	0
WreadyKnown_A	481407153	481203896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	481407153	23714096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	23714096	0	0
T1	11575	3287	0	0
T2	11715	3470	0	0
T3	8559	1312	0	0
T7	640056	108	0	0
T8	182133	114	0	0
T17	42574	939	0	0
T27	9285	108	0	0
T28	49260	1582	0	0
T29	11489	2229	0	0
T30	9208	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	23714096	0	0
T1	11575	3287	0	0
T2	11715	3470	0	0
T3	8559	1312	0	0
T7	640056	108	0	0
T8	182133	114	0	0
T17	42574	939	0	0
T27	9285	108	0	0
T28	49260	1582	0	0
T29	11489	2229	0	0
T30	9208	203	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483120171	30317387	0	0
DepthKnown_A	483120171	482861685	0	0
RvalidKnown_A	483120171	482861685	0	0
WreadyKnown_A	483120171	482861685	0	0
gen_passthru_fifo.paramCheckPass	2814	2814	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	30317387	0	0
T1	11575	12	0	0
T2	11715	12	0	0
T3	8559	12	0	0
T7	640056	81	0	0
T8	182133	105	0	0
T17	42574	226	0	0
T27	9285	20	0	0
T28	49260	309	0	0
T29	11489	13	0	0
T30	9208	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2814	2814	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T17	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483120171	41786986	0	0
DepthKnown_A	483120171	482861685	0	0
RvalidKnown_A	483120171	482861685	0	0
WreadyKnown_A	483120171	482861685	0	0
gen_passthru_fifo.paramCheckPass	2814	2814	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	41786986	0	0
T1	11575	12	0	0
T2	11715	12	0	0
T3	8559	12	0	0
T7	640056	81	0	0
T8	182133	491	0	0
T17	42574	692	0	0
T27	9285	106	0	0
T28	49260	309	0	0
T29	11489	41	0	0
T30	9208	141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2814	2814	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T17	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483120171	734391	0	0
DepthKnown_A	483120171	482861685	0	0
RvalidKnown_A	483120171	482861685	0	0
WreadyKnown_A	483120171	482861685	0	0
gen_passthru_fifo.paramCheckPass	2814	2814	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	734391	0	0
T4	175766	0	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	84	0	0
T18	34029	144	0	0
T19	11098	0	0	0
T20	0	23	0	0
T23	0	17	0	0
T27	9285	7	0	0
T28	49260	240	0	0
T29	11489	0	0	0
T30	9208	7	0	0
T81	0	4	0	0
T83	0	10	0	0
T85	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2814	2814	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T17	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483120171	1466823	0	0
DepthKnown_A	483120171	482861685	0	0
RvalidKnown_A	483120171	482861685	0	0
WreadyKnown_A	483120171	482861685	0	0
gen_passthru_fifo.paramCheckPass	2814	2814	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	1466823	0	0
T4	175766	0	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	241	0	0
T18	34029	144	0	0
T19	11098	0	0	0
T20	0	93	0	0
T23	0	68	0	0
T27	9285	31	0	0
T28	49260	240	0	0
T29	11489	0	0	0
T30	9208	29	0	0
T81	0	4	0	0
T83	0	10	0	0
T85	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2814	2814	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T17	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483120171	29526702	0	0
DepthKnown_A	483120171	482861685	0	0
RvalidKnown_A	483120171	482861685	0	0
WreadyKnown_A	483120171	482861685	0	0
gen_passthru_fifo.paramCheckPass	2814	2814	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	29526702	0	0
T1	11575	12	0	0
T2	11715	12	0	0
T3	8559	12	0	0
T7	640056	81	0	0
T8	182133	105	0	0
T17	42574	142	0	0
T27	9285	13	0	0
T28	49260	69	0	0
T29	11489	13	0	0
T30	9208	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2814	2814	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T17	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483120171	40320163	0	0
DepthKnown_A	483120171	482861685	0	0
RvalidKnown_A	483120171	482861685	0	0
WreadyKnown_A	483120171	482861685	0	0
gen_passthru_fifo.paramCheckPass	2814	2814	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	40320163	0	0
T1	11575	12	0	0
T2	11715	12	0	0
T3	8559	12	0	0
T7	640056	81	0	0
T8	182133	491	0	0
T17	42574	451	0	0
T27	9285	75	0	0
T28	49260	69	0	0
T29	11489	41	0	0
T30	9208	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483120171	482861685	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2814	2814	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T17	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T28,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T27,T28,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T27,T30,T17
1	1	0	Not Covered
1	1	1	Covered	T27,T28,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T27,T28,T30
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T27,T28,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481407153	1413629	0	0
DepthKnown_A	481407153	481203896	0	0
RvalidKnown_A	481407153	481203896	0	0
WreadyKnown_A	481407153	481203896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	481407153	1413629	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	1413629	0	0
T4	175766	0	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	241	0	0
T18	34029	144	0	0
T19	11098	0	0	0
T20	0	93	0	0
T23	0	68	0	0
T27	9285	31	0	0
T28	49260	240	0	0
T29	11489	0	0	0
T30	9208	29	0	0
T81	0	4	0	0
T83	0	10	0	0
T85	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	1413629	0	0
T4	175766	0	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	241	0	0
T18	34029	144	0	0
T19	11098	0	0	0
T20	0	93	0	0
T23	0	68	0	0
T27	9285	31	0	0
T28	49260	240	0	0
T29	11489	0	0	0
T30	9208	29	0	0
T81	0	4	0	0
T83	0	10	0	0
T85	0	29	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T28,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T27,T28,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T27,T28,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T27,T28,T30
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T27,T28,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481407153	551505	0	0
DepthKnown_A	481407153	481203896	0	0
RvalidKnown_A	481407153	481203896	0	0
WreadyKnown_A	481407153	481203896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	481407153	551505	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	551505	0	0
T4	175766	0	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	84	0	0
T18	34029	144	0	0
T19	11098	0	0	0
T20	0	15	0	0
T23	0	17	0	0
T27	9285	7	0	0
T28	49260	240	0	0
T29	11489	0	0	0
T30	9208	3	0	0
T80	0	18	0	0
T81	0	4	0	0
T85	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	551505	0	0
T4	175766	0	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	84	0	0
T18	34029	144	0	0
T19	11098	0	0	0
T20	0	15	0	0
T23	0	17	0	0
T27	9285	7	0	0
T28	49260	240	0	0
T29	11489	0	0	0
T30	9208	3	0	0
T80	0	18	0	0
T81	0	4	0	0
T85	0	8	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T27,T30,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T28,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T27,T28,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T27,T30,T17
1	1	0	Not Covered
1	1	1	Covered	T27,T28,T30

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T30

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T28,T30

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T27,T30,T17
1	0	Covered	T27,T28,T30
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T27,T28,T30
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T27,T28,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481407153	1154487	0	0
DepthKnown_A	481407153	481203896	0	0
RvalidKnown_A	481407153	481203896	0	0
WreadyKnown_A	481407153	481203896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	481407153	1154487	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	1154487	0	0
T4	175766	0	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	241	0	0
T18	34029	144	0	0
T19	11098	0	0	0
T20	0	63	0	0
T23	0	68	0	0
T27	9285	31	0	0
T28	49260	240	0	0
T29	11489	0	0	0
T30	9208	11	0	0
T80	0	18	0	0
T81	0	4	0	0
T85	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	481203896	0	0
T1	11575	11478	0	0
T2	11715	11645	0	0
T3	8559	8499	0	0
T7	640056	639999	0	0
T8	182133	182035	0	0
T17	42574	42476	0	0
T27	9285	9209	0	0
T28	49260	49177	0	0
T29	11489	11439	0	0
T30	9208	9132	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	481407153	1154487	0	0
T4	175766	0	0	0
T7	640056	0	0	0
T8	182133	0	0	0
T17	42574	241	0	0
T18	34029	144	0	0
T19	11098	0	0	0
T20	0	63	0	0
T23	0	68	0	0
T27	9285	31	0	0
T28	49260	240	0	0
T29	11489	0	0	0
T30	9208	11	0	0
T80	0	18	0	0
T81	0	4	0	0
T85	0	29	0	0