Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15667399	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16377750	1		T1	5225		T2	5		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31537186	1		T1	3000		T2	2		T3	2
values[0x0]	254145	1		T1	1245		T2	3		T3	5
values[0x1]	253818	1		T1	1280		T2	5		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12493127	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19552022	1		T1	5268		T2	6		T3	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	91391	1		T1	12		T5	124		T6	753
valid_sources[0x01]	104275	1		T1	23		T5	160		T6	678
valid_sources[0x02]	89356	1		T1	32		T5	164		T6	707
valid_sources[0x03]	96811	1		T1	10		T5	153		T6	742
valid_sources[0x04]	89759	1		T1	33		T5	159		T6	742
valid_sources[0x05]	88692	1		T5	124		T6	681		T9	2
valid_sources[0x06]	90213	1		T1	10		T5	164		T6	711
valid_sources[0x07]	331035	1		T1	58		T5	139		T6	731
valid_sources[0x08]	89278	1		T1	40		T5	140		T6	677
valid_sources[0x09]	226321	1		T1	3		T5	153		T6	749
valid_sources[0x0a]	308904	1		T1	40		T5	154		T6	678
valid_sources[0x0b]	93095	1		T1	44		T5	125		T6	713
valid_sources[0x0c]	649944	1		T1	27		T5	132		T6	739
valid_sources[0x0d]	88491	1		T1	12		T5	131		T6	700
valid_sources[0x0e]	90760	1		T1	16		T5	127		T6	731
valid_sources[0x0f]	89025	1		T1	10		T5	130		T6	708
valid_sources[0x10]	89334	1		T1	25		T5	150		T6	683
valid_sources[0x11]	90770	1		T1	15		T5	145		T6	681
valid_sources[0x12]	89388	1		T1	18		T5	147		T6	746
valid_sources[0x13]	89430	1		T1	29		T5	155		T6	684
valid_sources[0x14]	90117	1		T1	20		T5	152		T6	743
valid_sources[0x15]	89111	1		T1	28		T5	137		T6	735
valid_sources[0x16]	206056	1		T1	42		T5	172		T6	726
valid_sources[0x17]	89706	1		T1	9		T5	136		T6	738
valid_sources[0x18]	89987	1		T1	58		T5	185		T6	711
valid_sources[0x19]	115639	1		T1	7		T5	146		T6	719
valid_sources[0x1a]	112059	1		T1	23		T5	133		T6	697
valid_sources[0x1b]	91344	1		T1	32		T5	138		T6	698
valid_sources[0x1c]	89239	1		T1	5		T5	130		T6	693
valid_sources[0x1d]	207695	1		T1	11		T5	133		T6	637
valid_sources[0x1e]	90316	1		T1	19		T5	130		T6	677
valid_sources[0x1f]	174758	1		T1	30		T5	143		T6	750
valid_sources[0x20]	88279	1		T1	26		T5	137		T6	688
valid_sources[0x21]	89099	1		T5	125		T6	715		T31	2
valid_sources[0x22]	128079	1		T1	15		T5	127		T6	652
valid_sources[0x23]	91322	1		T1	12		T36	4		T5	131
valid_sources[0x24]	90058	1		T1	18		T5	118		T6	823
valid_sources[0x25]	89302	1		T1	13		T5	159		T6	743
valid_sources[0x26]	90518	1		T1	19		T5	136		T6	684
valid_sources[0x27]	155012	1		T1	7		T5	166		T6	693
valid_sources[0x28]	123234	1		T1	21		T3	6		T5	103
valid_sources[0x29]	88864	1		T1	26		T5	163		T6	767
valid_sources[0x2a]	92224	1		T1	12		T5	135		T6	757
valid_sources[0x2b]	89212	1		T1	18		T5	155		T6	707
valid_sources[0x2c]	128480	1		T1	50		T5	151		T6	683
valid_sources[0x2d]	188038	1		T1	10		T5	150		T6	680
valid_sources[0x2e]	89146	1		T1	17		T5	117		T6	691
valid_sources[0x2f]	90673	1		T1	17		T5	174		T6	715
valid_sources[0x30]	90017	1		T1	4		T5	171		T6	734
valid_sources[0x31]	90581	1		T1	8		T5	148		T6	677
valid_sources[0x32]	123845	1		T1	29		T5	122		T6	663
valid_sources[0x33]	89379	1		T1	17		T5	148		T6	688
valid_sources[0x34]	228349	1		T1	37		T5	130		T6	658
valid_sources[0x35]	90579	1		T1	32		T5	142		T6	700
valid_sources[0x36]	88637	1		T1	32		T5	111		T6	710
valid_sources[0x37]	90328	1		T1	12		T5	154		T37	4
valid_sources[0x38]	90005	1		T1	23		T5	161		T6	687
valid_sources[0x39]	89592	1		T1	28		T5	137		T6	723
valid_sources[0x3a]	90134	1		T1	25		T5	126		T6	685
valid_sources[0x3b]	89009	1		T1	11		T5	121		T6	702
valid_sources[0x3c]	90812	1		T1	30		T5	138		T6	729
valid_sources[0x3d]	287916	1		T1	11		T5	148		T6	770
valid_sources[0x3e]	88523	1		T1	31		T5	147		T6	717
valid_sources[0x3f]	89036	1		T1	15		T5	157		T6	693
valid_sources[0x40]	118172	1		T1	19		T5	155		T6	674
valid_sources[0x41]	90682	1		T1	33		T5	140		T6	706
valid_sources[0x42]	89254	1		T1	25		T5	154		T6	710
valid_sources[0x43]	90997	1		T1	37		T5	127		T6	661
valid_sources[0x44]	90077	1		T1	19		T5	129		T6	696
valid_sources[0x45]	90495	1		T1	46		T36	4		T5	123
valid_sources[0x46]	115678	1		T1	27		T5	145		T6	682
valid_sources[0x47]	92057	1		T1	4		T5	141		T6	704
valid_sources[0x48]	205868	1		T1	12		T3	1		T5	152
valid_sources[0x49]	90190	1		T1	12		T5	167		T6	668
valid_sources[0x4a]	410511	1		T1	30		T5	150		T6	734
valid_sources[0x4b]	90151	1		T1	9		T5	154		T6	704
valid_sources[0x4c]	293348	1		T1	38		T5	134		T6	637
valid_sources[0x4d]	89698	1		T1	26		T5	136		T6	718
valid_sources[0x4e]	205090	1		T1	36		T5	128		T6	733
valid_sources[0x4f]	90270	1		T1	33		T5	134		T6	728
valid_sources[0x50]	88836	1		T1	4		T5	127		T6	726
valid_sources[0x51]	96772	1		T1	2		T5	131		T6	726
valid_sources[0x52]	327280	1		T1	34		T5	137		T6	717
valid_sources[0x53]	359254	1		T1	41		T5	158		T6	690
valid_sources[0x54]	108588	1		T1	33		T5	149		T6	720
valid_sources[0x55]	89610	1		T1	6		T5	166		T6	724
valid_sources[0x56]	88732	1		T1	29		T5	154		T6	741
valid_sources[0x57]	90808	1		T1	29		T5	147		T6	700
valid_sources[0x58]	190927	1		T1	30		T5	136		T6	674
valid_sources[0x59]	89686	1		T1	48		T5	134		T6	747
valid_sources[0x5a]	152554	1		T1	9		T5	130		T6	725
valid_sources[0x5b]	90046	1		T1	17		T5	164		T6	730
valid_sources[0x5c]	114707	1		T1	35		T5	145		T6	707
valid_sources[0x5d]	90730	1		T1	25		T5	149		T6	710
valid_sources[0x5e]	89774	1		T1	11		T5	164		T6	722
valid_sources[0x5f]	91193	1		T1	31		T5	152		T6	722
valid_sources[0x60]	272744	1		T1	6		T5	167		T6	753
valid_sources[0x61]	90092	1		T1	16		T5	139		T6	676
valid_sources[0x62]	90404	1		T1	10		T5	137		T6	707
valid_sources[0x63]	88976	1		T1	4		T5	121		T6	745
valid_sources[0x64]	89681	1		T1	6		T5	147		T6	728
valid_sources[0x65]	180108	1		T1	15		T5	164		T6	710
valid_sources[0x66]	89557	1		T1	11		T5	163		T6	672
valid_sources[0x67]	89038	1		T1	20		T5	155		T37	6
valid_sources[0x68]	89639	1		T1	25		T5	167		T6	723
valid_sources[0x69]	236488	1		T1	17		T5	151		T6	731
valid_sources[0x6a]	89918	1		T1	33		T5	147		T6	728
valid_sources[0x6b]	89620	1		T1	29		T5	147		T6	710
valid_sources[0x6c]	89970	1		T1	5		T5	140		T6	667
valid_sources[0x6d]	111928	1		T1	8		T5	147		T6	720
valid_sources[0x6e]	97439	1		T1	11		T5	149		T6	777
valid_sources[0x6f]	90514	1		T1	12		T5	136		T6	751
valid_sources[0x70]	90214	1		T1	26		T5	136		T6	782
valid_sources[0x71]	89670	1		T1	5		T5	139		T6	704
valid_sources[0x72]	136660	1		T1	34		T5	128		T6	746
valid_sources[0x73]	90601	1		T1	6		T5	134		T6	770
valid_sources[0x74]	90816	1		T1	32		T5	126		T6	702
valid_sources[0x75]	90892	1		T1	62		T5	176		T6	681
valid_sources[0x76]	90618	1		T1	17		T2	1		T5	129
valid_sources[0x77]	90268	1		T1	12		T5	184		T6	763
valid_sources[0x78]	91847	1		T1	27		T5	144		T6	699
valid_sources[0x79]	90256	1		T1	22		T2	1		T5	126
valid_sources[0x7a]	108243	1		T1	7		T5	152		T6	688
valid_sources[0x7b]	129564	1		T1	22		T5	167		T6	704
valid_sources[0x7c]	89212	1		T1	22		T5	170		T6	772
valid_sources[0x7d]	89644	1		T1	52		T5	160		T6	723
valid_sources[0x7e]	89989	1		T1	35		T5	158		T6	684
valid_sources[0x7f]	89217	1		T1	22		T5	158		T6	704
valid_sources[0x80]	89511	1		T1	4		T2	1		T5	148

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15993211

1

T1

2876

T2

2

T36

1

values[0x0]

all_enables

biggest_size

200251

1

T1

1156

T2

1

T3

5

values[0x1]

all_enables

biggest_size

184288

1

T1

1193

T2

2

T36

3